Search - Turbo vhdl

[VHDL-FPGA-Verilog] Turbo VHDL

Description: VHDL源程序
Platform: | Size: 46569 | Author: adahwa | Hits:

[SourceCode] turbo码 IP core

Description: turbo码 IP core, VHDL编写，Altera公司的，用于信道编码中turbo码的译码
Platform: | Size: 155967 | Author: zhhzhhj@163.com | Hits:

[VHDL-FPGA-Verilog] gongcehngsheji_477-2

Description: 使用该VHDL在仿真软件中实现RSC(递归系统卷积)码的编码以及解码硬件仿真-use of the VHDL simulation software in achieving RSC (recursive convolution system) code encoding and decoding hardware simulation
Platform: | Size: 6144 | Author: 李超 | Hits:

[Communication-Mobile] turbo_VHDL

Description: Turbo Decoder Release 0.3 * Double binary, DVB-RCS code * Soft Output Viterbi Algorithm * MyHDL cycle/bit accurate model * Synthesizable VHDL model -Turbo Decoder Release 0.3* Double binary, DVB-RCS code* Soft Output Viterbi Algorithm* M yHDL cycle/bit accurate model* Synthesizable VHDL model
Platform: | Size: 154624 | Author: | Hits:

[Streaming Mpeg4] rs_enc

Description: 使用IP Core实现了3GPP/UMTS所规定的Turbo码编码，可以在Virtex全系列和Spartan-3E等芯片上使用，最多支持１６路信号，能提供3GPP所要求的1/3码率输出和可选的1/5码率输出-Use IP Core achieved 3GPP/UMTS provided for Turbo-Coded, you can Virtex series and Spartan-3E chip such as the use, supports up to 16-way signal, 3GPP can provide the required 1/3 bit-rate output and optional 1/5 Rate Output
Platform: | Size: 1024 | Author: 刘横 | Hits:

[VHDL-FPGA-Verilog] Turbo

Description: 基于fpga的交织编码器设计，主要讲叙如何在fpga上实现交织编码器。-something about turbo。
Platform: | Size: 1837056 | Author: xixi | Hits:

[Documents] Turbo

Description: 一种新的turbo码的交织编码器的vhdl设计，用的是螺旋输入。-something about turbo
Platform: | Size: 305152 | Author: xixi | Hits:

[Communication] control

Description: Turbo码编码器时序控制模块，能够对于RAM，ROM读写以及编码器其他功能模块的使能进行控制-Turbo code encoder timing control module, to the RAM, ROM reader and encoder modules, other functions can be controlled so that
Platform: | Size: 1024 | Author: sunhao | Hits:

[Communication-Mobile] encode_finish

Description: Turbo码编码器的encode最上层模块，它的主要作用是连接Turbo码编码器的其他模块-Turbo code encoder encode top-level module, its main role is to connect the Turbo Code encoder other modules
Platform: | Size: 1024 | Author: sunhao | Hits:

[Other] rom

Description: Turbo码编码器的Rom宏模块，此模块中包含Rom.v文件和存储交织地址的.mif文件-Turbo code encoder Rom macro module, this module contains intertwined Rom.v documents and store addresses. Mif file
Platform: | Size: 9216 | Author: sunhao | Hits:

[VHDL-FPGA-Verilog] RSC

Description: Turbo码编码器的两个分量编码器RSC，主要由四个移位寄存器和两个模2加法器组成-Turbo code encoder of the two component encoders RSC, mainly by the four shift register and the two-mode adder composed of 2
Platform: | Size: 1024 | Author: sunhao | Hits:

[Communication] Turbo

Description: 利用3GPP交织器和LTE交织器完成turbo码的仿真并做比较，不同解码算法的比较-Using 3GPP Interleaver and complete LTE interleaver turbo code simulation and comparison, a comparison of different decoding algorithms
Platform: | Size: 112640 | Author: 老五 | Hits:

[Software Engineering] FPGA_TEZ

Description: about fpga. turbo coding
Platform: | Size: 1899520 | Author: deniz | Hits:

[VHDL-FPGA-Verilog] turbocodes_latest.tar

Description: turbo encode and decoder
Platform: | Size: 83968 | Author: suresh | Hits:

[VHDL-FPGA-Verilog] EnergyEfficientVLSIArchitectureforLinearTurboEqua

Description: Energy efficient for turbo encoder decoder
Platform: | Size: 536576 | Author: suresh | Hits:

[VHDL-FPGA-Verilog] MapAlgorithm

Description: However, turbo equalizers can be computationally complex and hence require significant power consumption. In this paper, we present an energy-efficient VLSI architecture for such linear turbo equalizers. Key architectural techniques include elimination of redundant operations and early termination.
Platform: | Size: 1315840 | Author: suresh | Hits:

[VHDL-FPGA-Verilog] VerilogLangRefManual

Description: Simulation results show that energy savings in the range 30–60 and 10–60 are achieved in equalization and decoding, respectively. Furthermore, we present finite precision requirements of the linear turbo equalizer and an efficient rescaling method to prevent overflow.-Simulation results show that energy savings in the range 30–60 and 10–60 are achieved in equalization and decoding, respectively. Furthermore, we present finite precision requirements of the linear turbo equalizer and an efficient rescaling method to prevent overflow.
Platform: | Size: 1283072 | Author: suresh | Hits:

[VHDL-FPGA-Verilog] turbo

Description: turbo的VHDL代码比较好啊易后大家多多交流啊-Comparison of the VHDL code for turbo Well you lot of the easy exchange of ah
Platform: | Size: 153600 | Author: 秋晨 | Hits:

[VHDL-FPGA-Verilog] turbo

Description: Turbo仿真。VHDL语言。对学习编码很有帮助-Turbo
Platform: | Size: 8192 | Author: 朱宇容 | Hits:

[Other] turbo_VHDL

Description: Turbo码的VHDL描述，可以下载下来-VHDL description of Turbo Codes
Platform: | Size: 154624 | Author: qinlei | Hits:

« 12 3 »

Category

Source Code

Web/Internet

Develop Tools

Document

Other

Search in results

OS

Platform

Language

File Type

Search list

[VHDL-FPGA-Verilog] Turbo VHDL

[SourceCode] turbo码 IP core

[VHDL-FPGA-Verilog] gongcehngsheji_477-2

[Communication-Mobile] turbo_VHDL

[Streaming Mpeg4] rs_enc

[VHDL-FPGA-Verilog] Turbo

[Documents] Turbo

[Communication] control

[Communication-Mobile] encode_finish

[Other] rom

[VHDL-FPGA-Verilog] RSC

[Communication] Turbo

[Software Engineering] FPGA_TEZ

[VHDL-FPGA-Verilog] turbocodes_latest.tar

[VHDL-FPGA-Verilog] EnergyEfficientVLSIArchitectureforLinearTurboEqua

[VHDL-FPGA-Verilog] MapAlgorithm

[VHDL-FPGA-Verilog] VerilogLangRefManual

[VHDL-FPGA-Verilog] turbo

[VHDL-FPGA-Verilog] turbo

[Other] turbo_VHDL

CodeBus www.codebus.net