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Search - UART vhdl code for FPGA

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[VHDL-FPGA-Verilog] u-uart

Description: 一个可综合的串并转换接口verilog源代码-a comprehensive series of conversion and interface Verilog source code
Platform: | Size: 5120 | Author: 李文文 | Hits:

[VHDL-FPGA-Verilog] uart.core.for.FPGA

Description: 一个UART的FPGA core，附有详细的代码阅读笔记-A UART of the FPGA core, accompanied by a detailed code of reading notes
Platform: | Size: 614400 | Author: 获得 | Hits:

[SCM] new-lins-uart-all

Description: 无私奉献，VHDL 源码，用于实现FPGA上的UART(串口控制器)，可以实现FPGA与单片机，PC机的串口通讯。-Selfless dedication, VHDL source code for the FPGA realization of the UART (serial port controller), you can realize FPGA and MCU, PC serial communication machine.
Platform: | Size: 6144 | Author: 骑士 | Hits:

[VHDL-FPGA-Verilog] URAT_VHDL_CODE

Description: altera公司的fpga源代码，用VHDL编写的uart程序。-altera' s fpga source code, uart program written using VHDL.
Platform: | Size: 32768 | Author: 张东 | Hits:

[VHDL-FPGA-Verilog] UART

Description: 用FPGA开发的串口通信的程序，代码是用verilog编写的，希望对大家有用！-Serial communication with the FPGA development process, the code is written in verilog and hope for all of us!
Platform: | Size: 267264 | Author: 郭富民 | Hits:

[VHDL-FPGA-Verilog] uart_core(V2_0)

Description: 本例为自己编好的VHDL的基于uart的FPGA的 设计。-In this case for their own good VHDL code uart of FPGA-based design.
Platform: | Size: 2247680 | Author: xinlinrong | Hits:

[VHDL-FPGA-Verilog] gh_uart_16550_072108

Description: UART（通用串行收发器）的VHDL源代码，适合硬件工程师在FPGA内部实现多个UART-UART (universal serial transceivers), VHDL source code for hardware engineers in the FPGA to achieve multiple internal UART
Platform: | Size: 16384 | Author: 彭涛 | Hits:

[Com Port] uart

Description: Code VHDL/Verilog for UART FPGA: Xilinx, Altera-Code VHDL/Verilog for UART FPGA: Xilinx, Altera...
Platform: | Size: 11264 | Author: NgocAnh | Hits:

[VHDL-FPGA-Verilog] M130095EC

Description: vhdl code for uart. data tx from pc to fpga nd vice versa
Platform: | Size: 2288640 | Author: gaurav goyal | Hits:

[VHDL-FPGA-Verilog] UART-VHDL-Example-Code-for-an-FPGA-or-ASIC-from-n

Description: UART code using VHDL for FPGA or ASIC
Platform: | Size: 10240 | Author: dani | Hits:

[Other] kehshechenxu

Description: 编制一全双工UART电路，通过试验箱MAX202E转换成RS232电平，与计算机进行通讯实验，设置8个按键，按键值为ASIC码“1”~“8”，通过串口发送给计算机，在计算机上显示键值，同时在数码管最高位显示；计算机可发送“0”~“F”的ASIC码，FPGA接收后在数码管低位显示0~F。通过按键可设置波特率。 要求：波特率为三种 1200、2400、9600，由1个按键选择，3个LED分别指示； 数据格式为1位起始位、8位数据位和一位停止位； 上位计算机发送接收软件可使用“串口调试器“软件； 发送和接收数据时，由两个LED分别指示。 发挥：自动回发功能、接收到特殊字符（自定义）自动更改波特率。(A full duplex UART circuit, converted into RS232 level by MAX202E test box, communication experiment with computer, set of 8 buttons, keys for ASIC code "1" to "8", to the computer through the serial port to send and display keys on the computer, at the same time in the digital tube display high computer can send "; 0" to "F" in the ASIC code, FPGA after receiving the digital tube display low 0~F. You can set the baud rate by the button. Requirements: baud rate for three, 1200, 2400, 9600, selected by 1 buttons, 3 LED, respectively; The data format consists of 1 bit start bits, 8 bit data bits, and one stop bit; The upper computer sends and receives the software, and the serial debugger can be used; When sending and receiving data, instructions are given by two LED respectively. Play: Auto postback function, receive special characters (custom), change baud rate automatically.)
Platform: | Size: 2948096 | Author: 淡淡的意识 | Hits:

[VHDL-FPGA-Verilog] uart_working_transmit

Description: UART transmission vhdl code, for nexys 3 fpga board
Platform: | Size: 2254848 | Author: spiegel | Hits:

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