Search - USB Verilog

Search - USB Verilog - List

[VHDL-FPGA-Verilog] usb1.1_Verilog DL : 1: usb1.1的设备控制器IP核，是用verilog硬件描述语言写的-USB1.1 IP core for device control, written with hardware describing language of Verilog.
Update : 2025-02-17 Size : 128kb Publisher : 李恒
[Communication] 基于USB-ATA接口的海量存储器的设计与实现 DL : 0: 介绍了一种基于通用可编程接口的通用串行总线-高级技术配件解决方案，将普通硬盘转化为Usb Mass Storage.-introduces a general programmable interface based on the Universal Serial Bus-senior technical accessories solution that will drive into ordinary Usb Mass Storage.
Update : 2025-02-17 Size : 84kb Publisher : 蔡明
[VHDL-FPGA-Verilog] usb_funct DL : 0: usb1.0的核，有详细的usb核的设计源码，用verilog语言编写，同时附有相关的设计文档，质量不错-usb1.0 nuclear, nuclear usb detailed design source, using Verilog language, along with documents related to the design, quality good
Update : 2025-02-17 Size : 209kb Publisher :
[Other Embeded program] USB_yl DL : 0: 讲解USB接口原理： USB通信基本知识概要 USB的通讯协议 USB模块的编程方法 -USB interface on the principle : USB Communication outline basic knowledge of USB communication protocol modules USB Programming
Update : 2025-02-17 Size : 90kb Publisher :
[Com Port] usb_ctr DL : 0: usb的verilog 代码。对理解usb的原理有很大帮助，并可以在nc环境下仿真。-usb the Verilog code. Usb to understand the principle is very helpful, and to be nc simulation environment.
Update : 2025-02-17 Size : 52kb Publisher : hongbo
[USB develop] USB2_chip DL : 0: USB2.0 chip的一部分verilog源码。opencore上下的，还比较好用:)-USB2.0 chip part of Verilog source. Opencore ish, but also better quality :)
Update : 2025-02-17 Size : 35kb Publisher : 戴鹏
[USB develop] Usb_RTL(VHDL_Verilog) DL : 0: USBRTL电路的VHDL和Verilog代码-USBRTL Circuit VHDL and Verilog code
Update : 2025-02-17 Size : 262kb Publisher : 戴鹏
[VHDL-FPGA-Verilog] bfm DL : 0: Verilog HDL编写的总线功能模型，十分有用，需要的下载-Verilog HDL prepared by the bus functional model is useful, it needs to download
Update : 2025-02-17 Size : 2kb Publisher : wyl
[VHDL-FPGA-Verilog] usb1.1phy DL : 0: USB 1.1 PHY的代码，verilog语言 USB 1.1 PHY的代码，verilog语言-USB 1.1 PHY code, verilog language USB 1.1 PHY code, verilog language
Update : 2025-02-17 Size : 8kb Publisher : william
[VHDL-FPGA-Verilog] USB2.0IP_core_Verilog DL : 0: 完整的用VERILOG语言开发的USB2.0 IP核源代码，包括文档、仿真文件-complete with verilog language development USB2.0 IP source code, including documentation, Simulation documents
Update : 2025-02-17 Size : 202kb Publisher : 张清平
[ELanguage] usb_funct DL : 0: USB接口的VHDL源码，支持Verilog HDL程序-USB VHDL source code, supports Verilog HDL procedures
Update : 2025-02-17 Size : 225kb Publisher : 王森
[VHDL-FPGA-Verilog] usb_phy DL : 1: umti协议中的usb1.1的verilog原文件，可公实现usb2.0做参考-umti the agreement usb1.1 verilog the original documents, the public can refer to achieve usb2.0
Update : 2025-02-17 Size : 10kb Publisher : liuzefu
[VHDL-FPGA-Verilog] ccd-in-verilog DL : 0: ALTERA关于CCD的一些verilog程序，都通过运行无误的。-ALTERA on a number of Verilog CCD procedures, both by running unmistakable.
Update : 2025-02-17 Size : 14kb Publisher : 邹振兴
[VHDL-FPGA-Verilog] USB DL : 0: USB接口的测试程序，Verilog语言编写 -USB
Update : 2025-02-17 Size : 137kb Publisher : wzk
[VHDL-FPGA-Verilog] USB DL : 0: Verilog实现的USB程序，用ISE打开工程文件即可-Verilog implementation USB program, open the project file with the ISE can be
Update : 2025-02-17 Size : 137kb Publisher : Roy
[USB develop] pci-verilog DL : 0: USB及PCI总线设计的一些源代码（经测试）-USB and PCI bus design some of the source code
Update : 2025-02-17 Size : 421kb Publisher : tom
[Communication] verilog DL : 0: source code for USB 2.0 fonction core in verilog
Update : 2025-02-17 Size : 56kb Publisher : chaitanya
[VHDL-FPGA-Verilog] verilog-usb--protel-design DL : 1: 基于FPGA的usb2.0 ip核设计，所用的语言是verilog-FPGA-based usb2.0 ip core design, the language used is the verilog
Update : 2025-02-17 Size : 52kb Publisher : 唐明桂
[USB develop] module-usb DL : 0: usb verilog code for transmitter
Update : 2025-02-17 Size : 17kb Publisher : arun
[VHDL-FPGA-Verilog] usb DL : 0: USB的verilog IP模块，经过DesignCompiler综合验证-USB-verilog IP module, comprehensive verification through DesignCompiler
Update : 2025-02-17 Size : 56kb Publisher : sj

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