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[Embeded-SCM Develop] DE2_Default

Description: his design is the initial design when the board is powered-up. It increments a counter and displays the value on the 7-segment displays and LEDs. An image is also displayed on the VGA port.-his design is the initial design when the bo ard is powered-up. It increments a counter and d isplays the value on the 7-segment displays and LEDs. An image is also displayed on the VGA port.
Platform: | Size: 270233 | Author: 木 易 | Hits:

[Other resource] S3Demo

Description: Spartan 3 Digilent Demo:This demo drives the perphrials on the Spartan 3 board. This drives a simple pattern to the VGA port, connects the switches to the LEDs, buttons to each anode of the seven segment decoder. The seven segment decoder has a simple counter running on it, and when SW0 is in the up position the seven segment decoder will display scan codes from the PS2 port. This demo how ever does not drive the RS-232 port or the memory. This is a simple design done entirely VHDL not microblaze.
Platform: | Size: 731568 | Author: Roy Hsu | Hits:

[VHDL-FPGA-Verilog] DE2_D5M

Description: 在Quartus ii 10.0的环境下，实现了从D5M摄像头中读取Bayer数据并转化为RGB，通过SDRAM缓存，VGA控制器，输出到显示屏的Verilog代码-In Quartus ii 10.0 Read Bayer format from D5M camera and convert to RGB format, through SDRAM, output on VGA port.
Platform: | Size: 214016 | Author: Aaron | Hits:

[Embeded-SCM Develop] DE2_Default

Description: his design is the initial design when the board is powered-up. It increments a counter and displays the value on the 7-segment displays and LEDs. An image is also displayed on the VGA port.-his design is the initial design when the bo ard is powered-up. It increments a counter and d isplays the value on the 7-segment displays and LEDs. An image is also displayed on the VGA port.
Platform: | Size: 270336 | Author: 木 易 | Hits:

[VHDL-FPGA-Verilog] S3Demo

Description: Spartan 3 Digilent Demo:This demo drives the perphrials on the Spartan 3 board. This drives a simple pattern to the VGA port, connects the switches to the LEDs, buttons to each anode of the seven segment decoder. The seven segment decoder has a simple counter running on it, and when SW0 is in the up position the seven segment decoder will display scan codes from the PS2 port. This demo how ever does not drive the RS-232 port or the memory. This is a simple design done entirely VHDL not microblaze.
Platform: | Size: 731136 | Author: Roy Hsu | Hits:

[SCM] chezai_disp3

Description: keil打开-51单片机LCD显示程序 LCD控制模块使用深圳剑拓的串口转VGA模块-keil Open-51 Singlechip LCD display program LCD control module using the serial port of Shenzhen Jian Billiton to VGA Module
Platform: | Size: 166912 | Author: wanning | Hits:

[Embeded-SCM Develop] VgaTest

Description: CPLD驱动显示器的VGA口，程序比较简单，但是已经编译过的-CPLD driver display VGA port, the procedure is relatively simple, but has been compiled
Platform: | Size: 524288 | Author: wphyl | Hits:

[VHDL-FPGA-Verilog] pingball

Description: 这是一个带声音的弹球小游戏，通过VGA口显示，通过扩展口JA的 pin4和 pin GND输出声音， BTN3 BTN2 控制挡板左右移动，弹球和挡板都自带动画效果-This is a band sound pinball game, through the VGA port shows that through the expansion of the mouth of the JA and pin4 output pin GND voice, BTN3 BTN2 control baffle around Mobile, pinball and baffle all bring their own animation effects
Platform: | Size: 1126400 | Author: 瑞 | Hits:

[Other] vgadoc

Description: 比较详尽的VGA端口寄存器的文档，分类介绍了DOS下常用的VGA类型。在DOS下进行VGA编程必备。-A more detailed document VGA port registers, classification introduced commonly used VGA under DOS type. In DOS programming required under the VGA.
Platform: | Size: 350208 | Author: 天策 | Hits:

[Technology Management] VGA

Description: Send and image for the VGA port
Platform: | Size: 399360 | Author: oscard | Hits:

[VHDL-FPGA-Verilog] vgaoutfiles

Description: vhdl code for obtaining video output through vga port
Platform: | Size: 18432 | Author: isoft | Hits:

[VHDL-FPGA-Verilog] DE2_70_TV

Description: --- --- --- -Verilog--- --- ---- This design converts DVD video into a format suitable for display on a CRT/LCD monitor. A DVD video source, such as a DVD player, should be connected to the VIDEO IN port on the DE2-70 board. A CRT/LCD monitor should be connected to the VGA port. The DVD video should be displayed on the monitor. Initially, the video may be shifted vertically press KEY0 to force the design to resynchronize.--------------------Verilog---------------- This design converts DVD video into a format suitable for display on a CRT/LCD monitor. A DVD video source, such as a DVD player, should be connected to the VIDEO IN port on the DE2-70 board. A CRT/LCD monitor should be connected to the VGA port. The DVD video should be displayed on the monitor. Initially, the video may be shifted vertically press KEY0 to force the design to resynchronize.
Platform: | Size: 168960 | Author: Sami | Hits:

[VHDL-FPGA-Verilog] vga2

Description: VHDL code for UP2 board of Altera, that generate a video signal to VGA port.
Platform: | Size: 332800 | Author: Lokous | Hits:

[VHDL-FPGA-Verilog] DE2_NIOS_HOST_MOUSE_VGA

Description: 在DE2开发板上实现的VGA输出游戏。硬件用Verilog语言编写，在Quartus上编译；软件用C语言编写，在Nios2上编译运行。把DE2板和显示器键盘连起来即可使用。-Development in the DE2 board game to achieve the VGA output. Hardware using Verilog language, compiled in the Quartus software with C language, compiled to run in Nios2. The DE2 board and display can be used to connect the keyboard.
Platform: | Size: 1627136 | Author: 符玉襄 | Hits:

[Windows Develop] FPGAcode

Description: VGA ON DE2, this is the code for using the DE2 VGA port in oder to diplay picture.
Platform: | Size: 15360 | Author: mike | Hits:

[VHDL-FPGA-Verilog] main1

Description: vhdl code for vga port interfacing of spartan 3 (xilinx) displaying colour pattern
Platform: | Size: 6144 | Author: sachin | Hits:

[VHDL-FPGA-Verilog] vga

Description: SPARTAN3AN VGA test it s for starters to get the idea about how to use vga port on spartan3an kit. in this code , first 50mhz clock used to create a 25 mhz clock to use in vga snchronization . then a simple window is created on the screen -SPARTAN3AN VGA test it s for starters to get the idea about how to use vga port on spartan3an kit. in this code , first 50mhz clock used to create a 25 mhz clock to use in vga snchronization . then a simple window is created on the screen
Platform: | Size: 1024 | Author: gasd | Hits:

[VHDL-FPGA-Verilog] vgatutorial13

Description: 这个主要是用VHDL语言来实现从xilinxFPGA中的RBOM中读取一幅图像，并通过VGA口显示出来，同时还有加密的功能，按不同的按键可以实现图像颜色转换。-The VHDL language is mainly used in the RBOM from a xilinxFPGA to read an image, and displayed through the VGA port, as well as the function of encryption, the keys can be achieved by different image color conversion.
Platform: | Size: 1768448 | Author: 张元甲 | Hits:

[VHDL-FPGA-Verilog] vga

Description: This VHDL sample demonstrates how to generate a VGA signal to make it possible to connect an FPGA to a monitor. Written for Mimas v2, but probably easily adapted to any other board with a VGA connector on it (that can also be done by manually connecting a VGA port to a R-2R DAC and connecting that to GPIO: google for more information).
Platform: | Size: 1024 | Author: Ruben | Hits:

[VHDL-FPGA-Verilog] vga_test

Description: 用黑金板AX309实现对VGA口的控制，驱动显示器显示。程序基于ISE14.7，语言为Verilog。实测可用。(The black gold board AX309 realizes the control of the VGA port and drives the display of the display. The program is based on ISE14.7 and the language is Verilog. Measured available.)
Platform: | Size: 851968 | Author: 曹玄德 | Hits:
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