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[Crack Hack] 高级加密算法

Description: AES加密和解密源码！-AES encryption and decryption source!
Platform: | Size: 101376 | Author: 古月 | Hits:

[Crack Hack] AES算法完整源码

Description: AES算法完整源码-AES complete source
Platform: | Size: 225280 | Author: 天上人间 | Hits:

[Crack Hack] aes_encrypt

Description: AES加密软件，用于加密当前文本框中的内容。使用的是美国国家标准（也被ISO所采纳）最新加密算法AES。-AES encryption software, encryption for the current contents of the text box. The use of the American National Standards (also adopted by the ISO) the latest encryption algorithm AES.
Platform: | Size: 216064 | Author: | Hits:

[VHDL-FPGA-Verilog] AEScoremodules

Description: AES decoder aes_dec.vhdl AES encoder aes_enc.vhdl Package used by rest of design aes_pkg.vhdl Key Expansion component for AES encoder and decoder key_expansion.vhdl -AES AES encoder decoder aes_dec.vhdl aes_ enc.vhdl Package used by rest of design aes_pkg . vhdl Key Expansion component for a AES encoder nd decoder key_expansion.vhdl
Platform: | Size: 10240 | Author: 许茹芸 | Hits:

[MPI] fifo_vhd_131

Description: fifo vhdl源程序-fifo vhdl source
Platform: | Size: 15360 | Author: zlw | Hits:

[Crack Hack] aes_8bit

Description: VHDL实现128bitAES加密算法 LOW AREA节约成本的实现 DATA FLOW为8bits-VHDL realize 128bitAES encryption algorithm LOW AREA realize cost-saving DATA FLOW for 8 bits
Platform: | Size: 19456 | Author: ZHUOHUI LI | Hits:

[Crack Hack] aes_encryption

Description: aes加密算法的VHDL代码实现，在FPGA芯片上调试过-aes encryption algorithm realize the VHDL code in FPGA chips upward tried
Platform: | Size: 6144 | Author: stym_001 | Hits:

[VHDL-FPGA-Verilog] AES_RTL

Description: 使用Verilog HDL 實現AES硬體加解密-Realize the use of Verilog HDL hardware AES encryption and decryption
Platform: | Size: 15360 | Author: 林夢魔 | Hits:

[VHDL-FPGA-Verilog] CoreAES128

Description: Full AES Simulation Code
Platform: | Size: 1339392 | Author: esl | Hits:

[Crack Hack] RIJNDAEL_EN_TOP

Description: AES加密运算模块，运算速率100Mbps，请大家参考-AES encryption algorithms module, computing speed 100Mbps, please refer to
Platform: | Size: 16384 | Author: 刘文庆 | Hits:

[Crack Hack] RIJNDAEL_DE_TOP

Description: AES解密运算模块，运算速率100Mbps，请大家参考-AES decryption computing module, computing speed 100Mbps, please refer to
Platform: | Size: 19456 | Author: 刘文庆 | Hits:

[Crack Hack] aes

Description: aes加密算法实现，经过FPGA验证的！-aes encryption algorithm, after FPGA validation!
Platform: | Size: 6144 | Author: guochao | Hits:

[Crack Hack] aes_crypto_core_latest.tar

Description: Consecutive AES core Description of project.. Features - AES encoder - 128/192/256 bit - AES decoder - 128/192/256 bit Status - Key Expansion added - Encoder added - Decoder added - Documentation added
Platform: | Size: 961536 | Author: Arun | Hits:

[Crack Hack] AES

Description: AES算法的verilog代码，即AES算法IP核-ip core for AES
Platform: | Size: 13312 | Author: JJ | Hits:

[VHDL-FPGA-Verilog] aes

Description: vhdl implementation of the AES encryption algorithm
Platform: | Size: 244736 | Author: hesham | Hits:

[Crack Hack] mini_aes_latest[1].tar

Description: AES 加解密 代码, 有文档说明，testbench-AES encoding decoding source code in HDL
Platform: | Size: 233472 | Author: wangbin | Hits:

[VHDL-FPGA-Verilog] aes

Description: 实现了AES在赛灵思器件上的加密程序 我已经调试过完全正确-Xilinx achieved in AES encryption device debugging process I have been absolutely correct
Platform: | Size: 4096 | Author: wangrui | Hits:

[Algorithm] AES

Description: This the source code of AES algorithm which is used in network security.-This is the source code of AES algorithm which is used in network security.
Platform: | Size: 10240 | Author: Krupesh | Hits:

[VHDL-FPGA-Verilog] aes

Description: aes的加密解密算法的源代码以及测试源代码和仿真结果图-aes encryption decryption algorithm source code and test source code and simulation results map
Platform: | Size: 2973696 | Author: cong | Hits:

[VHDL-FPGA-Verilog] AES

Description: AES implementation in VHDL@!
Platform: | Size: 521216 | Author: manishrb | Hits:
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