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[Internet-Network] mii

Description: 以太网PHY端口MII物理层收发程序，可作为开发参考-MII Ethernet PHY port physical layer transceiver procedures, can be used as the development of reference
Platform: | Size: 18432 | Author: re | Hits:

[USB develop] usb_phy

Description: usb接口协议。It was tested with a USB 1.1 core I have written on a XESS XCV800 board with a a Philips PDIUSBP11A transceiver. -usb interface protocol. It was tested with a USB 1.1 core I have written ona XESS XCV800 board with aa Philips PDIUSBP11A transceiver.
Platform: | Size: 11264 | Author: 颜新卉 | Hits:

[Other] fpga_mac_vhdl

Description: 针对嵌入式系统的底层网络接口给出了一种由FPGA实现的以太网控制器的设计方法．该控制器能支持10Mbps和100Mbps的传输速率以及半双工和全双工模式，同时可提供MII接口，可并通过外接以太网物理层（PHY）芯片来实现网络接入 -Embedded systems for the bottom of this paper, a network interface from FPGA to achieve the Ethernet controller design method. The controller will support the 10Mbps and 100Mbps transfer rate, as well as half-duplex and full-duplex mode, at the same time provides MII interface, and through external Ethernet physical layer (PHY) chip to achieve network access
Platform: | Size: 316416 | Author: 林大朋 | Hits:

[VHDL-FPGA-Verilog] usb_phy.tar

Description: Very simple USB 1.1 PHY. Includes all the goodies: serial/parallel conversion, bit stuffing/unstuffing, NRZI encoding decoding. Uses a simplified UTMI interface. Currently doesn t do any error checking in the RX section [should probably check for bit unstuffing errors]. Otherwise complete and fully functional. There is currently no test bench available. This core is very simple and is proven in hardware. I see no point of writing a test bench at this time.
Platform: | Size: 7168 | Author: eldis | Hits:

[VHDL-FPGA-Verilog] mdio-md

Description: 目前以太网PHY芯片是通过总线MDC/MDIO，但是基本上是通过MAC芯片直接管理的，本代码实现了通过FPGA管理PHY。即由FPGA完成MII管理-At present, Ethernet PHY chip through the bus MDC/MDIO, but basically through the direct management of MAC chip, the code through the FPGA implementation management PHY. FPGA completed by the MII management
Platform: | Size: 2048 | Author: leon | Hits:

[Embeded-SCM Develop] pcie_vera_tb_latest.tar

Description: FEATURES • 16 bit PIPE Spec PCI Express Testbench • Link training • Initial Flow Control • Packet Classes for easy to build PHY,DLLP and TLP packets • DLLP 16 bit CRC and TLP LCRC generation • Sequence Number generation and checking • ACK TLP packets • Scrambling • MemRd MemWr CfgRd CfgWr TLPs -FEATURES • 16 bit PIPE Spec PCI Express Testbench • Link training • Initial Flow Control • Packet Classes for easy to build PHY,DLLP and TLP packets • DLLP 16 bit CRC and TLP LCRC generation • Sequence Number generation and checking • ACK TLP packets • Scrambling • MemRd MemWr CfgRd CfgWr TLPs
Platform: | Size: 169984 | Author: Arun | Hits:

[USB develop] USB2.0

Description: UTMI全称为 USB2.0 Transceiver Macrocell Interface，此协议是针对USB2.0的信号特点进行定义的，分为8位或16位数据接口。目的是为了减少开发商的工作量，缩短产品的设计周期，降低风险。此接口模块主要是处理物理底层的USB协议及信号，可与SIE整合设计成一专用ASIC芯片，也可独立作为PHY的收发器芯片，下以8位接口为例介绍PHY的工作原理及设计特点。 -UTMI called USB2.0 Transceiver Macrocell Interface, this agreement is a signal for USB2.0-defined characteristics, is divided into 8-bit or 16-bit data interface. The purpose is to reduce the workload of developers to shorten product design cycles, reduce risk. This interface module is mainly to deal with the underlying physics of the USB protocol and signaling, can be integrated with the SIE designed a dedicated ASIC chips, can also be independent of the transceiver as a PHY chip, the next eight to PHY interface as an example to introduce the working principle and design features.
Platform: | Size: 210944 | Author: leixueyan | Hits:

[Internet-Network] Mac_Phy_IF

Description: 物理层和MAC层的接口控制文件，主要管理两层之间的时序控制-Physical layer and MAC layer interface control documents, the main management of the timing between two-tier control
Platform: | Size: 2048 | Author: 小贝 | Hits:

[Embeded-SCM Develop] 802.11_PHY_PLCP

Description:
Platform: | Size: 106496 | Author: 何波 | Hits:

[Books] bmul32par

Description: scrambler for IEEE 802.16 PHY
Platform: | Size: 1024 | Author: user1 | Hits:

[VHDL-FPGA-Verilog] usb_latest.tar

Description: 用VHDL语言编写的USB 2.0IP核。USB 2.0的传输速率是高速率480 Mb/s，需要再外扩一个PHY。-This is a USB 2.0 compliant core，USB 2.0 allows data transfers of 480 Mb/s. Because of the high interface speed, an external PHY will be required with this core.
Platform: | Size: 196608 | Author: liang | Hits:

[Other] intit

Description: 初始化网络芯片，我负责的是MAC的初始化和PHY初始化。可以试着在此基础上编写以太网。-Initialize the network chip, I am responsible for the MAC and PHY initialization initialization. Can try to write on this basis Ethernet.
Platform: | Size: 2048 | Author: 张见平 | Hits:

[Windows Develop] ECMA-369

Description:
Platform: | Size: 623616 | Author: zhouli | Hits:

[VHDL-FPGA-Verilog] DX-PHY

Description: ddr phy design spec and example-ddr phy design spec and example!!
Platform: | Size: 250880 | Author: yangxf | Hits:

[VHDL-FPGA-Verilog] mdio

Description: MDIO verilog RTL代码，SOC可以通过MDIO接口来访问外部PHY等慢速外设-MDIO verilog RTL code
Platform: | Size: 4096 | Author: dingyy | Hits:

[VHDL-FPGA-Verilog] ofdmbaseband

Description: the OFDM PHY is adaptive therefore it supports multiple schemes BPSK, QPSK, 16-QAM and 64-QAM for data carriers’ modulation. The constellation diagrams are gray mapped and shows the magnitudes I and Q (In-phase and Quadrature) components of each incoming bit(s) combination along with their normalization factor C to calculate magnitude of each model
Platform: | Size: 1497088 | Author: san | Hits:

[VHDL-FPGA-Verilog] scrambler-wimax

Description: This package contains synthesizable VHDL codes for scramber/descrambler module for IEEE 802.16 WiMAX PHY layer.
Platform: | Size: 1024 | Author: zpatel | Hits:

[Software Engineering] USB1.1-VHDL

Description: USB PHY RX DPLL This source file may be used and distributed without restriction provided that this copyright statement is not removed from the file and that any derivative work contains the original copyright notice and the associated disclaimer.-USB PHY RX DPLL This source file may be used and distributed without restriction provided that this copyright statement is not removed from the file and that any derivative work contains the original copyright notice and the associated disclaimer.
Platform: | Size: 6144 | Author: LJ | Hits:

[VHDL-FPGA-Verilog] MII

Description: 以太网MII芯片配置接口的VHDL设计，配置PHY芯片的模块设计-Ethernet MII chip configuration interface VHDL design, configuration PHY chip module design
Platform: | Size: 2048 | Author: 雷伟林 | Hits:

[VHDL-FPGA-Verilog] PHY_DD6

Description: 10/100 Base-T Ethernet PHY test for Spartan-6 on microblaze processor.
Platform: | Size: 11630592 | Author: kilometrix | Hits:
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