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[VHDL-FPGA-Verilog] spi slave

Description: SPI 接口的VHDL和Verilog实现。slave模式
Platform: | Size: 4132 | Author: szsz06@126.com | Hits:

[VHDL-FPGA-Verilog] spi

Description: VHDL实现SPI功能源代码 -- The SPI bus is a 3 wire bus that in effect links a serial shift -- register between the "master" and the "slave". Typically both the -- master and slave have an 8 bit shift register so the combined -- register is 16 bits. When an SPI transfer takes place, the master and -- slave shift their shift registers 8 bits and thus exchange their 8 -- bit register values.-SPI realize the functional VHDL source code The SPI bus is a 3 wire bus that in effect links a serial shift register between the
Platform: | Size: 65536 | Author: 阿飞 | Hits:

[Embeded-SCM Develop] vspi_VHDL

Description: FPGA/CPLD VHDL语言实现SPI，拥有两种模式，FPGA/CPLD即可工作在主机模式，又可工作在从机模式 -FPGA/CPLD VHDL language SPI, have the two models, FPGA/CPLD can work in host mode, but also work in slave mode
Platform: | Size: 248832 | Author: 张焱 | Hits:

[SCM] SPI

Description: // This program accesses a SPI EEPROM using polled mode access. The F06x MCU // is configured in 4-wire Single Master Mode, and the EEPROM is the only // slave device connected to the SPI bus. The read/write operations are // tailored to access a Microchip 4 kB EEPROM 25LC320. The relevant hardware // connections of the F06x MCU are shown here:
Platform: | Size: 72704 | Author: 蓝天 | Hits:

[Embeded-SCM Develop] SPI

Description: spi slave model spi slave model
Platform: | Size: 1024 | Author: jason | Hits:

[VHDL-FPGA-Verilog] SimpleSpi

Description: SPI接口VHDL代码,内有说明,很详细.-SPI interface VHDL code, which has made it clear that, in great detail.
Platform: | Size: 180224 | Author: dushibiao | Hits:

[Embeded-SCM Develop] spi_slave

Description: spi slave 8bit address 1bit r/w 7bit number data
Platform: | Size: 155648 | Author: im | Hits:

[Other] spi.tar

Description: This is a verilog code used oversampled clock to implement SPI slave. Also include C code for a ARM processor as the SPI master-This is a verilog code used oversampled clock to implement SPI slave
Platform: | Size: 1024 | Author: johnl | Hits:

[SCM] SPI_vrilog

Description: SPI接口源码,语言vrilog,包括MASTER和SLAVE-SPI interf for vrilog.
Platform: | Size: 3072 | Author: linno | Hits:

[Other] spi_slave

Description: SPI slave source code
Platform: | Size: 351232 | Author: Chris | Hits:

[Embeded-SCM Develop] spi_slave

Description: Simple SPI slave with MOSI MISO SCLK SS signals
Platform: | Size: 1024 | Author: Aymen Bouach | Hits:

[Embeded-SCM Develop] SPI_TEST

Description: The Serial Peripheral Interface Bus or SPI bus is a synchronous serial data link standard named by Motorola that operates in full duplex mode. Devices communicate in master/slave mode where the master device initiates the data frame. Multiple slave devices are allowed with individual slave select (chip select) lines. Sometimes SPI is called a "four wire" serial bus, contrasting with three, two, and one wire serial buses.-The Serial Peripheral Interface Bus or SPI bus is a synchronous serial data link standard named by Motorola that operates in full duplex mode. Devices communicate in master/slave mode where the master device initiates the data frame. Multiple slave devices are allowed with individual slave select (chip select) lines. Sometimes SPI is called a "four wire" serial bus, contrasting with three, two, and one wire serial buses.
Platform: | Size: 478208 | Author: wei | Hits:

[Software Engineering] conjoined

Description: SPI protocol: Serial Periphral Interface with both slave and master incorporated-SPI protocol: Serial Periphral Interface with both slave and master incorporated
Platform: | Size: 1024 | Author: smik | Hits:

[VHDL-FPGA-Verilog] l1ghVhVI

Description: The VSPI core implements an SPI interface compatible with the many -- serial EEPROMs, and microcontrollers. The VSPI core is typically used -- as an SPI master, but it can be configured as an SPI slave as well.
Platform: | Size: 226304 | Author: aaa | Hits:

[VHDL-FPGA-Verilog] VHD_Veri_spi

Description: 一个强大的符合SPI规范的VHDL/Verilog源码文件，传输模式和时钟相位均可以指定，采用同步时钟设计，可以工作在很高的频率下。支持主机及从机模式，强烈推荐使用！-A strong line with SPI standard VHDL/Verilog source files, transfer mode, and clock phase are to specify, using synchronous clock design can work in very high frequency. Support the host and slave mode, strongly recommended!
Platform: | Size: 13312 | Author: 中国 | Hits:

[VHDL-FPGA-Verilog] spi

Description: Altera Cyclone SPI-slave vhdl module
Platform: | Size: 491520 | Author: xornonop | Hits:

[VHDL-FPGA-Verilog] spi_slave_test

Description: 实现spi协议的从机代码，亲测可用。按照字节接收，发送可以实现一次发送19字节，可按照需要更改。(The implementation of the code of the SPI slave protocol is available. By byte received, sending can be sent to send 19 bytes at a time, which can be changed as needed.)
Platform: | Size: 1008640 | Author: fantastic_guy | Hits:

[VHDL-FPGA-Verilog] VHDL_SPISLAVE

Description: spi-slave通信的vhdl实现及其仿真(VHDL implementation of spi-slave communication)
Platform: | Size: 760832 | Author: 马尔科姚 | Hits:

[Other] spi

Description: 利用VHDL在FPGA内实现SPI总线的主从控制器设计(SPI Master and Slave Controller)
Platform: | Size: 638976 | Author: 今世闲人 | Hits:

[VHDL-FPGA-Verilog] spi_slave

Description: 使用VHDL语言写的程序，利用SPI协议实现串并转换电路(Programs written in VHDL language and series-to-parallel conversion circuit implemented by SPI protocol)
Platform: | Size: 4470784 | Author: umbrella0923 | Hits:
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