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[Other resource] 567

Description: The paper presents the CORDIC Algorithm, which has been implemented as an virtual component (IP core) in a VHDL simulation environment. The core is packaged as a soft (VHDL) macro and it implements all transcenden-tal functions. Analysis of the accuracy of the algorithms implemented shows that the CORDIC functions are equivalent to the accuracy of a Pentium coprocessor.
Platform: | Size: 117831 | Author: 赵平 | Hits:

[Software Engineering] 567

Description: The paper presents the CORDIC Algorithm, which has been implemented as an virtual component (IP core) in a VHDL simulation environment. The core is packaged as a soft (VHDL) macro and it implements all transcenden-tal functions. Analysis of the accuracy of the algorithms implemented shows that the CORDIC functions are equivalent to the accuracy of a Pentium coprocessor.
Platform: | Size: 117760 | Author: 赵平 | Hits:

[VHDL-FPGA-Verilog] t80.tar

Description: T80处理器VHDL语言描述，可在FPGA中虚拟T80处理机-T80 processor described in VHDL language can be virtual FPGA Processor T80
Platform: | Size: 41984 | Author: 陈楚龙 | Hits:

[VHDL-FPGA-Verilog] CPLDtemperatureinthefiredetectionsystemof

Description: 介绍了光纤光栅感温火灾探测系统的应用原 理，并重点阐述了用CPLD 设计虚拟MC14499 器件模 块，给出并解释了用Verilog HDL 语言实现的部分程 序和仿真测试结果。-Introduction of Fiber Bragg Grating temperature fire detection system principles, and focuses on the use of CPLD design virtual MC14499 device module, are given and explained using the Verilog HDL language to achieve some of the procedures and simulation test results.
Platform: | Size: 345088 | Author: hjh | Hits:

[Graph program] smart

Description: 这个一个好和序，一个美丽学校的虚拟现实，此程序很好！-This a good and order, a Beauty School of virtual reality, this program very good!
Platform: | Size: 9216 | Author: 何渊泽 | Hits:

[VHDL-FPGA-Verilog] computer4

Description: 基于FPGA的CPU核及其虚拟平台的设计与实现-FPGA-based CPU core and its virtual platform design and implementation of
Platform: | Size: 6060032 | Author: steven | Hits:

[ARM-PowerPC-ColdFire-MIPS] ug_virtual_jtag_design_example_2

Description: 包含两的关于Virtual JTAG的应用实例，可以为Virtual JTAG操作提供借鉴。-Contains two Virtual JTAG on the application, can provide reference Virtual JTAG operation.
Platform: | Size: 311296 | Author: youthl | Hits:

[ARM-PowerPC-ColdFire-MIPS] ug_virtual_jtag_design_example_1

Description: 包含两的关于Virtual JTAG的应用实例，可以为Virtual JTAG操作提供借鉴。-Contains two Virtual JTAG on the application, can provide reference Virtual JTAG operation.
Platform: | Size: 143360 | Author: youthl | Hits:

[Other] Virtualdevicesandvirtualinterfacemodel

Description: 虚拟器件和虚拟接口模型verilog实现-Virtual devices and virtual interface model verilog implementation
Platform: | Size: 263168 | Author: shenmi | Hits:

[Embeded-SCM Develop] UART

Description: A simple preoteus based design to display the characters typed int the keyboard into LCD using UART of 8051.Plz make sure that TTL to RS232 is inserted in between the microcontroller and virtual terminal which is not shown in the design.
Platform: | Size: 45056 | Author: sandeep | Hits:

[VHDL-FPGA-Verilog] vc

Description: virtul channel 虚拟通道 用于改善noc的死锁效应-virtul channel virtual channel used to improve the effect of noc Deadlock
Platform: | Size: 11264 | Author: 长华 | Hits:

[VHDL-FPGA-Verilog] PIPE_LINING_CPU_TEAM_24

Description: 采用Quatus II编译环境，使用Verilog HDL语言编写实现了五段流水线CPU。 能够完成以下二十二条指令（均不考虑虚拟地址和Cache，并且默认为小端方式）： add rd,rs,rt addu rd,rs,rt addi rt,rs,imm addiu rt,rs,imm sub rd,rs,rt subu rd,rs,rt nor rd,rs,rt xori rt,rs,imm clo rd,rs clz rd,rs slt rd,rs,rt sltu rd,rs,rt slti rt,rs,imm sltiu rt,rs,imm sllv rd,rt,rs sra rd,rt,shamt blez rs,imm j target lwl rt,offset(base) lwl rt,offset(base) lw rt,imm(rs) sw rt,imm(rs) 在本设计中，采取非常良好的模块化编程风格，共分十三个主要模块PIPE_LINING_CPU_TEAM_24.v为顶层实体文件，对应为PIPE_LINING_CPU_TEAM_24模块作为顶层实体模块，如下： ifetch.v、regdec.v、exec.v、mem.v、wr.v分别实现五个流水段； cpuctr.v用于产生CPU控制信号； ALU.v用于对操作数进行相应指令的运算并输出结果； DM.v数据存储器 IM.v指令存储器 datareg.v数据寄存器堆 extender.v位扩展 yiwei_32bits.v 实现32位四种移位方式的移位器 在顶层实体中，调用ifetch.v、regdec.v、exec.v、mem.v、wr.v这五个模块就实现了流水线CPU。顶层模块的结构清晰明了。对于学习verilog编程非常有用- Quatus II compiled by the environment, using Verilog HDL language to achieve a five-stage pipeline CPU. To complete the following 22 commands (not considering the virtual address and Cache, and the default mode for the small end): add rd, rs, rt addu rd, rs, rt addi rt, rs, imm addiu rt, rs, imm sub rd, rs, rt subu rd, rs, rt nor rd, rs, rt xori rt, rs, imm clo rd, rs clz rd, rs slt rd, rs, rt sltu rd, rs, rt slti rt, rs, imm sltiu rt, rs, imm sllv rd, rt, rs sra rd, rt, shamt blez rs, imm j target lwl rt, offset (base) lwl rt, offset (base) lw rt, imm (rs) sw rt, imm (rs) In this design, take a very good modular programming style, is divided into 13 main modules PIPE_LINING_CPU_TEAM_24.v for the top-level entity file, the corresponding module as a top-level entity for the PIPE_LINING_CPU_TEAM_24 modules, as follows: ifetch.v, regdec.v, exec.v, mem.v, wr.v water were to achieve the five paragraph cpuctr.v used to generate CPU control signal ALU.v accordingly
Platform: | Size: 4946944 | Author: 石 | Hits:

[VHDL-FPGA-Verilog] Sdram_Control_2Port

Description: 双端口SDRAM控制器，将SDRAM虚拟成两个端口，已经在ALTER DE2开发板的硬件上验证通过，采用Verilog HDL语言编写。-Dual-port SDRAM controller, SDRAM virtual into two ports, have ALTER DE2 development board hardware verification by using the Verilog HDL language.
Platform: | Size: 11264 | Author: | Hits:

[Software Engineering] multifreqvhdl

Description: 资料是本人根据相关文献资料用vhdl语言编写的旋转机械鉴相信号倍频的程序，multifre1.vhd是倍频程序，multifre1.vwf是仿真波形文件，stp1.stp是虚拟逻辑分析仪signaltap文件。该倍频程序可以直接使用，可以设置倍频数，修改实体参数N即可。-According to the literature data is the information I have written in with vhdl Rotating Machinery Kam believe that the procedure multiplier number, multifre1.vhd is the multiplier process, multifre1.vwf is the simulation waveform files, stp1.stp a virtual logic analyzer signaltap file. The multiplier process can be used directly, you can set the multiplier number, modify the parameter N can be solid.
Platform: | Size: 1433600 | Author: lwj | Hits:

[Internet-Network] VLAN_data_process

Description: VLAN虚拟局域网的数据收发详细过程 图文并茂-VLAN Virtual LAN data transceiver illustrated detailed process
Platform: | Size: 208896 | Author: 李明 | Hits:

[VHDL-FPGA-Verilog] vmware-1

Description: 一个虚拟机的全部注册教程我都舍不得上传的-All up a virtual machine I am reluctant to upload tutorial
Platform: | Size: 11264 | Author: 彭庆 | Hits:

[VHDL-FPGA-Verilog] PipelineCPU

Description: 用Verilog HDL语言或VHDL语言来编写，实现多周期CPU设计。能够完成以下二十二条指令。（均不考虑虚拟地址和Cache，并且默认为大端方式）： add rd, rs, rt addu rd, rs, rt addi rt, rs, imm addiu rt, rs, imm sub rd, rs, rt subu rd, rs, rt nor rd, rs, rt xori rt, rs, imm clo clz slt rd, rs, rt sltu rd, rs, rt slti rt, rs, imm sltiu rt, rs, imm sllv rd，rt，rs sra rd，rt，shamt blez rs, imm j target lwl rt，offset（base） lwr rt，offset（base） lw rt，imm（rs） sw rt，imm（rs） -Written in Verilog HDL or VHDL language, multi-cycle CPU design. Able to complete the following 22 instructions. (Not taking into account the virtual address and the Cache, and the default is big endian): add rd, rs, rt addu rd, rs, rt addi rt, rs, imm addiu rt, rs, imm sub rd, rs, rt subu rd, rs, rt of nor rd, rs, rt xori rt, rs, imm clo clz slt rd, rs, rt sltu rd, rs, rt slti rt, rs, imm sltiu rt, rs, imm sllv rd, rt, rs sra rd, rt, shamt blez rs, imm j target lwl rt, offset (base) lwr rt, offset (base) lw rt, imm (rs) sw rt, imm (rs)
Platform: | Size: 5079040 | Author: 徐帆 | Hits:

[VHDL-FPGA-Verilog] mulitcpu

Description: 用verilog HDL语言或者VHDL语言来编写，实现多时钟周期CPU的设计。能够完成以下二十二条指定（均不考虑虚拟地址和Cache，并且默认为小端方式）： add rd, rs, rt addu rd, rs, rt addi rt, rs, imm addiu rt, rs, imm sub rd, rs, rt subu rd, rs, rt nor rd, rs, rt xori rt, rs, imm clo clz slt rd, rs, rt sltu rd, rs, rt slti rt, rs, imm sltiu rt, rs, imm sllv rd, rt, rs sra rd, rt, shamt blez rs, imm j target lwl rt, offset(base) lwr rt, offset(base) lw rt, imm(rs) sw rt, imm(rs) -Verilog HDL language or VHDL language to write multi-clock cycle of the CPU design. To complete the following 22 specified (not taking into account the virtual address and the Cache and the default Xiaoduan): add rd, rs, rt addu rd, rs, rt addi rt, rs, imm addiu rt, rs, imm sub rd, rs, rt subu rd, rs, rt of nor rd, rs, rt xori rt, rs, imm clo clz slt rd, rs, rt sltu rd, rs, rt slti rt, rs, imm sltiu rt, rs, imm sllv rd, rt, rs sra rd, rt, shamt blez rs, imm j target lwl rt, offset (base) lwr rt, offset (base) lw rt, imm (rs) sw rt, imm (rs)Undo edits DictionaryGoogle Translate for Business:Translator ToolkitWebsite TranslatorGlobal Market Finder
Platform: | Size: 8877056 | Author: 徐帆 | Hits:

[Software Engineering] Radar-on-FPGA

Description: 主要论述了基于FPGA的末制导雷达伺服系统设计。结合末制导雷达讨论其电机控制、二阶伺服系统性能和PID校正算法,利用VHDL语言设计,实现基于FPGA的方位步进电机开环定位控制和俯仰直流电机闭环速度控制的伺服系统。结合实际应用中遇到的问题,提出了基于"反馈控制"理论的有效的补偿算法,该算法提高了伺服系统的稳定性、快速性和精度。-Mainly discusses the design of terminal guidance radar servo system based on Field Programmable Gates Array(FPGA).It includes the system’s electric machine control,second-order servo system performance and PID correction algorithm based on Virtual Hardware Description Language(VHDL) on azimuth stepping motor open loop positioning control and pitch direct current electric machine closed loop speed control of the FPGA servo system.In allusion to some factual problems during its application,presents corresponding effective solutions based on traditional control theory "Feedback Control".The fact proves that these methods can greatly improve the stability,speediness and precision of the original servo system.Additionally,a basic algorithm which can be realized in a terminal guidance radar servo system is given
Platform: | Size: 1137664 | Author: mabeibei | Hits:

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