Description: Quatus II compiled by the environment, using Verilog HDL language to achieve a five-stage pipeline CPU.
To complete the following 22 commands (not considering the virtual address and Cache, and the default mode for the small end):
add rd, rs, rt addu rd, rs, rt addi rt, rs, imm addiu rt, rs, imm sub rd, rs, rt
subu rd, rs, rt nor rd, rs, rt xori rt, rs, imm clo rd, rs clz rd, rs
slt rd, rs, rt sltu rd, rs, rt slti rt, rs, imm sltiu rt, rs, imm sllv rd, rt, rs
sra rd, rt, shamt blez rs, imm j target lwl rt, offset (base)
lwl rt, offset (base) lw rt, imm (rs) sw rt, imm (rs)
In this design, take a very good modular programming style, is divided into 13 main modules PIPE_LINING_CPU_TEAM_24.v for the top-level entity file, the corresponding module as a top-level entity for the PIPE_LINING_CPU_TEAM_24 modules, as follows:
ifetch.v, regdec.v, exec.v, mem.v, wr.v water were to achieve the five paragraph
cpuctr.v used to generate CPU control signal
ALU.v accordingly
- [Calculator_1024] - This is a realization of the grammar use
- [cache] - original verilog HDL achieve CACHE opera
- [niosII_system_cpu] - cpu code, can be accomplished under the
- [waterline_adder] - This is a Verilog prepared with four pip
- [vc] - virtul channel virtual channel used to i
- [PipelineCPU] - This file is written in Verilog to achie
- [cache] - cache verilog
- [071221088] - Implement a simple single-cycle pipeline
- [CPU] - Pipelined 32-bit MIPS-based CPU, by them
- [liushuixianCPU] - VHDL design of pipelined CPU based on Qu
File list (Check if you may need any files):
PIPE_LINING_CPU_TEAM_24\ALU.v
.......................\ALU.v.bak
.......................\cpuctr.v
.......................\cpuctr.v.bak
.......................\datareg.v
.......................\datareg.v.bak
.......................\.b\PIPE_LINING_CPU_TEAM_24.asm.qmsg
.......................\..\PIPE_LINING_CPU_TEAM_24.cbx.xml
.......................\..\PIPE_LINING_CPU_TEAM_24.cmp.bpm
.......................\..\PIPE_LINING_CPU_TEAM_24.cmp.cdb
.......................\..\PIPE_LINING_CPU_TEAM_24.cmp.ecobp
.......................\..\PIPE_LINING_CPU_TEAM_24.cmp.hdb
.......................\..\PIPE_LINING_CPU_TEAM_24.cmp.kpt
.......................\..\PIPE_LINING_CPU_TEAM_24.cmp.logdb
.......................\..\PIPE_LINING_CPU_TEAM_24.cmp.rdb
.......................\..\PIPE_LINING_CPU_TEAM_24.cmp.tdb
.......................\..\PIPE_LINING_CPU_TEAM_24.cmp0.ddb
.......................\..\PIPE_LINING_CPU_TEAM_24.cmp_merge.kpt
.......................\..\PIPE_LINING_CPU_TEAM_24.db_info
.......................\..\PIPE_LINING_CPU_TEAM_24.eco.cdb
.......................\..\PIPE_LINING_CPU_TEAM_24.eds_overflow
.......................\..\PIPE_LINING_CPU_TEAM_24.fit.qmsg
.......................\..\PIPE_LINING_CPU_TEAM_24.hier_info
.......................\..\PIPE_LINING_CPU_TEAM_24.hif
.......................\..\PIPE_LINING_CPU_TEAM_24.lpc.html
.......................\..\PIPE_LINING_CPU_TEAM_24.lpc.rdb
.......................\..\PIPE_LINING_CPU_TEAM_24.lpc.txt
.......................\..\PIPE_LINING_CPU_TEAM_24.map.bpm
.......................\..\PIPE_LINING_CPU_TEAM_24.map.cdb
.......................\..\PIPE_LINING_CPU_TEAM_24.map.ecobp
.......................\..\PIPE_LINING_CPU_TEAM_24.map.hdb
.......................\..\PIPE_LINING_CPU_TEAM_24.map.kpt
.......................\..\PIPE_LINING_CPU_TEAM_24.map.logdb
.......................\..\PIPE_LINING_CPU_TEAM_24.map.qmsg
.......................\..\PIPE_LINING_CPU_TEAM_24.map_bb.cdb
.......................\..\PIPE_LINING_CPU_TEAM_24.map_bb.hdb
.......................\..\PIPE_LINING_CPU_TEAM_24.map_bb.logdb
.......................\..\PIPE_LINING_CPU_TEAM_24.pre_map.cdb
.......................\..\PIPE_LINING_CPU_TEAM_24.pre_map.hdb
.......................\..\PIPE_LINING_CPU_TEAM_24.rpp.qmsg
.......................\..\PIPE_LINING_CPU_TEAM_24.rtlv.hdb
.......................\..\PIPE_LINING_CPU_TEAM_24.rtlv_sg.cdb
.......................\..\PIPE_LINING_CPU_TEAM_24.rtlv_sg_swap.cdb
.......................\..\PIPE_LINING_CPU_TEAM_24.sgate.rvd
.......................\..\PIPE_LINING_CPU_TEAM_24.sgate_sm.rvd
.......................\..\PIPE_LINING_CPU_TEAM_24.sgdiff.cdb
.......................\..\PIPE_LINING_CPU_TEAM_24.sgdiff.hdb
.......................\..\PIPE_LINING_CPU_TEAM_24.sim.cvwf
.......................\..\PIPE_LINING_CPU_TEAM_24.sim.hdb
.......................\..\PIPE_LINING_CPU_TEAM_24.sim.qmsg
.......................\..\PIPE_LINING_CPU_TEAM_24.sim.rdb
.......................\..\PIPE_LINING_CPU_TEAM_24.sld_design_entry.sci
.......................\..\PIPE_LINING_CPU_TEAM_24.sld_design_entry_dsc.sci
.......................\..\PIPE_LINING_CPU_TEAM_24.syn_hier_info
.......................\..\PIPE_LINING_CPU_TEAM_24.tan.qmsg
.......................\..\PIPE_LINING_CPU_TEAM_24.tis_db_list.ddb
.......................\..\PIPE_LINING_CPU_TEAM_24.tmw_info
.......................\..\PIPE_LINING_CPU_TEAM_24_global_asgn_op.abo
.......................\..\prev_cmp_PIPE_LINING_CPU_TEAM_24.asm.qmsg
.......................\..\prev_cmp_PIPE_LINING_CPU_TEAM_24.fit.qmsg
.......................\..\prev_cmp_PIPE_LINING_CPU_TEAM_24.map.qmsg
.......................\..\prev_cmp_PIPE_LINING_CPU_TEAM_24.qmsg
.......................\..\prev_cmp_PIPE_LINING_CPU_TEAM_24.sim.qmsg
.......................\..\prev_cmp_PIPE_LINING_CPU_TEAM_24.tan.qmsg
.......................\..\wed.wsf
.......................\DM.v
.......................\DM.v.bak
.......................\exec.v
.......................\exec.v.bak
.......................\extender.v
.......................\extender.v.bak
.......................\ifetch.v
..............
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