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[Other] rs-codec-8-16

Description: 这是一个rs译码器的verilog程序运行于quatus-This is a rs decoder running on Verilog quatus
Platform: | Size: 132096 | Author: yuanfeng | Hits:

[Other] Crack_QII72_b151

Description: Crack_QII72_b151 is quatus ii used for fpga.
Platform: | Size: 7171 | Author: hewen1983 | Hits:

[Other resource] taxi

Description: 在Quatus下用VerilogHDL语言编写，实现出租车计价器功能
Platform: | Size: 381148 | Author: baohaitao | Hits:

[Other resource] RS232

Description: quatus II 环境下vhdl实现RS232功能
Platform: | Size: 437869 | Author: 王艳华 | Hits:

[Other resource] Quartusii

Description: 郑亚民版的可编程逻辑器件开发软件quatus ii里的一些例程，对初学者很有帮助。
Platform: | Size: 9295664 | Author: 王廷龙 | Hits:

[Other resource] seven_segment

Description: 以QuatusⅡ为平台，用HVDL语言实现7段数码管译码器的功能。
Platform: | Size: 101341 | Author: cheng sonja | Hits:

[Other resource] LOCK

Description: 以QuatusⅡ为平台，采用VHDL语言实现数字密码锁的功能，可以仿真实现。
Platform: | Size: 188061 | Author: cheng sonja | Hits:

[Other resource] DE2_with_VGA_LCM

Description: altera de2 开发板 vga lcd控制quatus 工程
Platform: | Size: 2924382 | Author: 李志 | Hits:

[Other] rs-codec-8-16

Description: 这是一个rs译码器的verilog程序运行于quatus-This is a rs decoder running on Verilog quatus
Platform: | Size: 133120 | Author: yuanfeng | Hits:

[Other] Crack_QII72_b151

Description: Crack_QII72_b151 is quatus ii used for fpga.
Platform: | Size: 7168 | Author: hewen1983 | Hits:

[VHDL-FPGA-Verilog] taxi

Description: 在Quatus下用VerilogHDL语言编写，实现出租车计价器功能-VerilogHDL in Quatus using language to achieve functional Taximeter
Platform: | Size: 380928 | Author: baohaitao | Hits:

[VHDL-FPGA-Verilog] RS232

Description: quatus II 环境下vhdl实现RS232功能-quatus II environment realize RS232 VHDL functional
Platform: | Size: 437248 | Author: 王艳华 | Hits:

[VHDL-FPGA-Verilog] Quartusii

Description: 郑亚民版的可编程逻辑器件开发软件quatus ii里的一些例程，对初学者很有帮助。-Asia and China Zheng version of programmable logic device quatus ii software development, some routines useful for beginners.
Platform: | Size: 9295872 | Author: 王廷龙 | Hits:

[SCM] seven_segment

Description: 以QuatusⅡ为平台，用HVDL语言实现7段数码管译码器的功能。-Quatus Ⅱ as a platform to use language to achieve HVDL digital tube 7 decoder functions.
Platform: | Size: 101376 | Author: cheng sonja | Hits:

[VHDL-FPGA-Verilog] LOCK

Description: 以QuatusⅡ为平台，采用VHDL语言实现数字密码锁的功能，可以仿真实现。-To Quatus Ⅱ as a platform, the use of VHDL language digital code lock function, you can realize simulation.
Platform: | Size: 187392 | Author: cheng sonja | Hits:

[VHDL-FPGA-Verilog] DE2_with_VGA_LCM

Description: altera de2 开发板 vga lcd控制quatus 工程-altera de2 board vga lcd control quatus works
Platform: | Size: 2924544 | Author: 李志 | Hits:

[Communication-Mobile] Digital_filterin_code

Description: MATLAB辅助设计数字滤波器源代码，QUATUS II 实现！-MATLAB-aided design of digital filter source code, QUATUS II implementation!
Platform: | Size: 66560 | Author: 五木 | Hits:

[VHDL-FPGA-Verilog] Quartus_Common_Error_And_Warning_Analyze

Description: Quatus常见错误汇总与分析 该文章来源 :一是来自网上几处出处的汇总 二是来自作者本人应用过程中遇到的问题。 可以帮助大家解决烦人的quartus警告和error 仅供参考 -Summary and analysis of common mistakes Quatus the article Source: First, a summary of provenance from the Internet a few second is from the author and the problems encountered in the application process. Can help you solve the annoying warnings and error in quartus reference
Platform: | Size: 15360 | Author: 龙也 | Hits:

[Other] vhdl_sram_ctrl

Description: Sycronous SRAM in CPLD or FPGA module... tested by Altera MaxPlusII or Quatus -Sycronous SRAM in CPLD or FPGA module... tested by Altera MaxPlusII or Quatus II
Platform: | Size: 1024 | Author: hanhyunjin | Hits:

[VHDL-FPGA-Verilog] PIPE_LINING_CPU_TEAM_24

Description: 采用Quatus II编译环境，使用Verilog HDL语言编写实现了五段流水线CPU。 能够完成以下二十二条指令（均不考虑虚拟地址和Cache，并且默认为小端方式）： add rd,rs,rt addu rd,rs,rt addi rt,rs,imm addiu rt,rs,imm sub rd,rs,rt subu rd,rs,rt nor rd,rs,rt xori rt,rs,imm clo rd,rs clz rd,rs slt rd,rs,rt sltu rd,rs,rt slti rt,rs,imm sltiu rt,rs,imm sllv rd,rt,rs sra rd,rt,shamt blez rs,imm j target lwl rt,offset(base) lwl rt,offset(base) lw rt,imm(rs) sw rt,imm(rs) 在本设计中，采取非常良好的模块化编程风格，共分十三个主要模块PIPE_LINING_CPU_TEAM_24.v为顶层实体文件，对应为PIPE_LINING_CPU_TEAM_24模块作为顶层实体模块，如下： ifetch.v、regdec.v、exec.v、mem.v、wr.v分别实现五个流水段； cpuctr.v用于产生CPU控制信号； ALU.v用于对操作数进行相应指令的运算并输出结果； DM.v数据存储器 IM.v指令存储器 datareg.v数据寄存器堆 extender.v位扩展 yiwei_32bits.v 实现32位四种移位方式的移位器 在顶层实体中，调用ifetch.v、regdec.v、exec.v、mem.v、wr.v这五个模块就实现了流水线CPU。顶层模块的结构清晰明了。对于学习verilog编程非常有用- Quatus II compiled by the environment, using Verilog HDL language to achieve a five-stage pipeline CPU. To complete the following 22 commands (not considering the virtual address and Cache, and the default mode for the small end): add rd, rs, rt addu rd, rs, rt addi rt, rs, imm addiu rt, rs, imm sub rd, rs, rt subu rd, rs, rt nor rd, rs, rt xori rt, rs, imm clo rd, rs clz rd, rs slt rd, rs, rt sltu rd, rs, rt slti rt, rs, imm sltiu rt, rs, imm sllv rd, rt, rs sra rd, rt, shamt blez rs, imm j target lwl rt, offset (base) lwl rt, offset (base) lw rt, imm (rs) sw rt, imm (rs) In this design, take a very good modular programming style, is divided into 13 main modules PIPE_LINING_CPU_TEAM_24.v for the top-level entity file, the corresponding module as a top-level entity for the PIPE_LINING_CPU_TEAM_24 modules, as follows: ifetch.v, regdec.v, exec.v, mem.v, wr.v water were to achieve the five paragraph cpuctr.v used to generate CPU control signal ALU.v accordingly
Platform: | Size: 4946944 | Author: 石 | Hits:
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