Search - VHDL calculator

[VHDL-FPGA-Verilog] codeofvhdl2006

Description: 【经典设计】VHDL源代码下载～～其中经典的设计有：【自动售货机】、【电子钟】、【红绿灯交通信号系统】、【步进电机定位控制系统】、【直流电机速度控制系统】、【计算器】、【点阵列LED显示控制系统】基本数字逻辑设计有：【锁存器】、【多路选择器】、【三态门】、【双向输入|输出端口】、【内部（缓冲）信号】、【编码转换】、【加法器】、【编码器/译码器】、【4位乘法器】、【只读存储器】、【RSFF触发器】、【DFF触发器】、【JKFF触发器】、【计数器】、【分频器】、【寄存器】、【状态机】 - [ Classics design ] the VHDL source code downloads ~ ~ classics the design to include: [ Vending machine ], [ electron clock ], [ traffic light traffic signal system ], [ step of 杩涚數 machine localization control system ], [ direct current machine speed control system ], [ calculator ], [ array LED display control system ] the basic numeral logical design includes: [ Latch ], [ multichannel selector ], [ 涓夋
Platform: | Size: 44032 | Author: senkong | Hits:

[VHDL-FPGA-Verilog] calculation2

Description: 用VHDL语言实现0--100范围内简单计算器功能的源代码，包括加减乘除四种运算功能-VHDL 0-- 100 within a simple calculator function in the source code. including the four arithmetic operations function
Platform: | Size: 2048 | Author: 刘西圣 | Hits:

[VHDL-FPGA-Verilog] calculator

Description: 用VHDL编写的计算器，能实现简单的加减乘除四则运算
Platform: | Size: 21504 | Author: huyanlong | Hits:

[Embeded-SCM Develop] calculator

Description: 学习嵌入式必须的东西，能够让你学起来是事半功倍，信不信你自己下了-Embedded learning to be something that allows you to learn from them is much more effective, believe it or not you own a
Platform: | Size: 304128 | Author: mamou | Hits:

[Other] VHDL1

Description: a simple calculator with vhdl operators performing calculator operation
Platform: | Size: 1024 | Author: mak chi ho | Hits:

[Other] comp

Description: 计算器显示部分的7段译码管。输入四位的二进制端口，输出7位的译码端口-Calculator shows that part of paragraph 7 decoding tube. Binary four input ports, output port 7 of the decoding
Platform: | Size: 2048 | Author: 妃儿 | Hits:

[Other] MultipleNumbersCalculator

Description: Multiple Numbers Calculator (source code and LAB notes)
Platform: | Size: 1017856 | Author: eknngx | Hits:

[VHDL-FPGA-Verilog] 61EDA_D1051

Description: 用VHDL编写的计算器：能实现简单的加减乘除四则运算-Prepared using VHDL calculator: to achieve simple addition and subtraction, multiplication and division four computing
Platform: | Size: 24576 | Author: 缺打打 | Hits:

[VHDL-FPGA-Verilog] erwertwerwe

[VHDL-FPGA-Verilog] 1

Description: 用VHDL编写的计算器：能实现简单的加减乘除四则运算 -Prepared using VHDL Calculator: able to achieve simple addition and subtraction, multiplication and division 4 computing
Platform: | Size: 4096 | Author: 邓法群 | Hits:

[VHDL-FPGA-Verilog] jisuanqi

Description: 用VHDL语言实现通用计算器设计，MUXPLUS2软件仿真验证-Implementation using VHDL language design generic calculator, MUXPLUS2 software simulation to verify
Platform: | Size: 1067008 | Author: DAVID | Hits:

[Other] jishuqi

Description: 描述的是一个带有异步复位和同步时钟使能的十进制加法计算器,-With reset and clock enable decimal calculator
Platform: | Size: 29696 | Author: 谭海洋 | Hits:

[Windows Develop] NewFolder

Description: calculator program is a good program
Platform: | Size: 5120 | Author: abison | Hits:

[VHDL-FPGA-Verilog] shifter

Description: 移位运算器SHIFTER 使用Verilog HDL 语言编写，其输入输出端分别与键盘/显示器LED 连接。移位运算器是时序电路，在J钟信号到来时状态产生变化， CLK 为其时钟脉冲。由S0、S1 、M 控制移位运算的功能状态，具有数据装入、数据保持、循环右移、带进位循环右移，循环左移、带进位循环左移等功能。 CLK 是时钟脉冲输入，通过键5 产生高低电平M 控制工作模式， M=l 时带进位循环移位，由键8 控制CO 为允许带进位移位输入，由键7 控制:S 控制移位模式0-3 ，由键6 控制，显示在数码管LED8 上 D[7..0]是移位数据输入，由键2 和1 控制，显示在数码管2 和1 上 QB[7..0]是移位数据输出，显示在数码管6 和5 上:cn 是移位数据输出进位，显示在数码管7 上。-SHIFTER shift calculator using Verilog HDL language, the input and output side with the keyboard/display LED connection. Shift operator is a sequential circuit, in J when the bell signals the arrival of a state of change, CLK its clock. By S0, S1, M to control the functions of the state of shift operations, with data loading, data maintenance, cycle shifted to right, into the digital cycle shifted to right, circle left, circle to the left into the digital functions. CLK is the clock pulse input through the key high 5 low M mode control, M = l-bit cyclic shift into when, controlled by the key 8 into the displacement of CO to allow input from 7 control keys: S Control Shift Mode 0-3, 6 button control from showing in the digital control LED8 on D [7 .. 0] is the shift data input from the keys 2 and 1 control, displayed in the digital tube 2 and 1 QB [7. .0] is the displacement data output, displayed on the LED 6 and 5: cn is a binary data output shift, showing 7 on in the digital co
Platform: | Size: 129024 | Author: 623902748 | Hits:

[VHDL-FPGA-Verilog] subadd

Description: 一个四位二进制加/减运算器。要求：当控制端G＝0时做加运算，G＝1时做减运算。用发光二极管表示运算结果的正、负。用数码管显示运算结果：加运算时，相加之和不超过15，减运算时，结果可正可负，但都用原码表示。-Plus a four binary/by calculator. Requirements: When the control terminal G = 0 when computing increases, G = 1 when computing reduced. Computing with light-emitting diodes, said the results of positive and negative. Digital display computing Results: Canadian operations, the sum of not more than 15, by calculation, the result can be negative now, but they said the original code.
Platform: | Size: 224256 | Author: 张三 | Hits:

[VHDL-FPGA-Verilog] calculator_vhdl

Description: Design PC calculator controlled by PC, using FPGA .PC and FPGA are connected by USB. -Design PC calculator controlled by PC, using FPGA .PC and FPGA are connected by USB.
Platform: | Size: 3501056 | Author: song | Hits:

[VHDL-FPGA-Verilog] yetert

Description: This package includes 4-bit calculator designed in Xilinx FPGA 10 using VHDL. This calculator contains 3 registers, 1 ALU, 1 decoder and 1 FSM (finite state machine).
Platform: | Size: 458752 | Author: crion | Hits:

[Software Engineering] calculator

Description: calculator, sin ,cos,multi, loga,-calculator, sin ,cos,multi, loga,...
Platform: | Size: 3163136 | Author: khanh | Hits:

[VHDL-FPGA-Verilog] calculator

Description: VHDL编写计算器，功能包括：加，减，乘，除。通过keypad输入及输出-Calculator written with VHDL
Platform: | Size: 314368 | Author: hodog | Hits:

[VHDL-FPGA-Verilog] calculator

Description: 用VHDL在quartus2下实现的计算器。输入为4*4矩阵键盘，输出为共用数据线的数码管。可以实现简单数学运算、逻辑运算、进制转换、连续运算等功能。-Using VHDL in quartus2 achieve calculator. Input 4* 4 matrix keyboard, the output data lines for sharing of digital control. Can achieve a simple mathematical operations, logical operations, binary conversion, continuous operations and other functions.
Platform: | Size: 1276928 | Author: jizhen | Hits:

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[VHDL-FPGA-Verilog] codeofvhdl2006

[VHDL-FPGA-Verilog] calculation2

[VHDL-FPGA-Verilog] calculator

[Embeded-SCM Develop] calculator

[Other] VHDL1

[Other] comp

[Other] MultipleNumbersCalculator

[VHDL-FPGA-Verilog] 61EDA_D1051

[VHDL-FPGA-Verilog] erwertwerwe

[VHDL-FPGA-Verilog] 1

[VHDL-FPGA-Verilog] jisuanqi

[Other] jishuqi

[Windows Develop] NewFolder

[VHDL-FPGA-Verilog] shifter

[VHDL-FPGA-Verilog] subadd

[VHDL-FPGA-Verilog] calculator_vhdl

[VHDL-FPGA-Verilog] yetert

[Software Engineering] calculator

[VHDL-FPGA-Verilog] calculator

[VHDL-FPGA-Verilog] calculator

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