Description: This the source code of AES algorithm which is used in network security.-This is the source code of AES algorithm which is used in network security. Platform: |
Size: 10240 |
Author:Krupesh |
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Description: 用verilog代码实现JPEG压缩编码过程中的DCT模块，用移位加法实现了乘法-Verilog code using JPEG compression encoding process to achieve the DCT module, with the shift to achieve the multiplication addition Platform: |
Size: 2048 |
Author:jiang |
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Description: Matlab code to simulation the wireless channel type.This is the most common case called Rayleigh channel.And in the frequency selective channel. Platform: |
Size: 8192 |
Author:allen |
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Description: 基于FPGA的AES算法实现的VERILOG源代码，对于信息安全专业研究AES算法的硬件实现很有用-FPGA-based AES algorithm implementation VERILOG source code, for the information security professional research of the hardware implementation of AES algorithm is useful Platform: |
Size: 195584 |
Author:李华 |
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Description: 此课件是基于FPGA的加密芯片设计实例，DES的FPGA实现，包括DES加密算法简述，DES的伪代码描述，设计流程，运算电路模型设计，算法程序设计
-The courseware is based on the FPGA chip design example of encryption, DES for FPGA implementation, including the DES encryption algorithm briefly, DES pseudo-code description of the design process, operation circuit modeling, algorithm programming Platform: |
Size: 3852288 |
Author:betty |
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Description: 本文介绍了AES加密算法通过不同的功能结构的FPGA实现，语言背景为VHDL-This paper details Implementation of the Encryption algorithm AES under VHDL language In FPGA by
using different architecture of mixcolumn. We then review this research investigates the AES algorithm in
FPGA and the Very High Speed Integrated Circuit Hardware Description language (VHDL). Altera
Quartus II software is used for simulation and optimization of the synthesizable VHDL code. The set of
transformations of both Encryptions and decryption are simulated using an iterative design approach in
order to optimize the hardware consumption. Altera Cyclone III Family devices are utilized for hardware uation. Platform: |
Size: 191488 |
Author:Eric |
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Description: We present an efficient hardware architecture design & implementation of Advanced Encryption Standard AES Rijndael cryptosystem. The AES algorithm defined by the National Institute of Standard and Technology NIST of United States has been widely accepted. All the cryptographic algorithms developed can be implemented with software or built with pure hardware. However with the help of Field Programmable Gate Arrays FPGA we tend to find expeditious solution and which can be easily upgraded to integrateany concordat changes. This contribution investigates the AES encryption and decryption cryptosystem with regard to FPGA and Very High Speed Integrated Circuit Hardware Description language VHDL. Optimized and Synthesizable VHDL code is developed for the implementation of both 128-bit data encryption and decryption process. Platform: |
Size: 27648 |
Author:kutti
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