Search - VHDL ddr2

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[OS program] ddr2 VHDL原代码 DL : 0: ddr2的仿真代码
Update : 2009-09-02 Size : 813.8kb Publisher : kabtechnology@126.com
[ARM-PowerPC-ColdFire-MIPS] Altera的IP源码8237 DL : 0: 名鼎鼎的Synopsys公司出的8051IP Core VHDL语言编写，能被keilC51支持-renowned name of the company Synopsys 8051IP Core VHDL language, support can be keilC51
Update : 2025-02-17 Size : 203kb Publisher : 上面的
[Graph Drawing] VGAsingl DL : 0: fpga显示控制器，利用vhdl语言实现，只能显示8色。-fpga display controller, using vhdl language, the only shows that eight colors.
Update : 2025-02-17 Size : 1kb Publisher : lyc
[Compress-Decompress algrithms] DDR2_sdram DL : 0: DDR2 的控制器，它是由LATTICE的编译器生成。-DDR2 controller, it is by the compiler-generated LATTICE.
Update : 2025-02-17 Size : 944kb Publisher : 李国
[VHDL-FPGA-Verilog] DDR2_module_VHDL_test(Rev0.1) DL : 0: ddr 2 接口读写测试模块 ddr 2 接口读写测试模块 -ddr 2 interface test module ddr 2 read and write interface to read and write test module
Update : 2025-02-17 Size : 123kb Publisher : 骑士
[Other] LVDS DL : 0: 关于lvds的详细介绍和讨论，非常适合初学者使用-LVDS details on the presentations and discussions, is very suitable for beginners to use
Update : 2025-02-17 Size : 87kb Publisher : 周洲
[VHDL-FPGA-Verilog] zbt_rd_vhdl_str_v1.0.0 DL : 0: ddr2 controller功能控制,里面有四个模块-ddr2 controller functions to control, which has four modules
Update : 2025-02-17 Size : 1.61mb Publisher : li ji wei
[VHDL-FPGA-Verilog] DDR2Controller DL : 0: DDR2 Controller DDR2 Controller
Update : 2025-02-17 Size : 305kb Publisher : tg
[VHDL-FPGA-Verilog] ddr2sdram_spartan3s700an.tar DL : 0: It is a first time code being developed to designers who want to get your DDR2 SDRAM on-board in Spartan 3AN Starter Kit - Diligent fully working.-It is a first time code being developed to designers who want to get your DDR2 SDRAM on-board in Spartan 3AN Starter Kit- Diligent fully working.
Update : 2025-02-17 Size : 1.42mb Publisher : under
[VHDL-FPGA-Verilog] OpenSPARC_DDR2_controller_RTL_Files DL : 0: 基于FPGA的DDR2控制程序，用verilog编写的。-FPGA-based DDR2 control procedures, prepared by using Verilog.
Update : 2025-02-17 Size : 30kb Publisher : 王头
[Embeded-SCM Develop] ddr_ddr2_sdram DL : 0: 基于NIOS II的ddr2控制器,配有详细的文档,经验证后可使用.-NIOS II based on the DDR2 controller, equipped with detailed documentation, the experience can be used after certification.
Update : 2025-02-17 Size : 3.33mb Publisher : Jackie
[Software Engineering] fpga-pinball_for_c DL : 0: VHDL 基于FPGA 和VGA 接口的应用设计-vhdl
Update : 2025-02-17 Size : 218kb Publisher : xietianjiao
[Other] CODE DL : 0: DDR2源代码 DDR2源代码-ddr2 source code ddr2 source code ddr2 source code
Update : 2025-02-17 Size : 292kb Publisher : 司炯
[Other] Micron_DDR DL : 0: DDR2 SDRAM 颗粒初始化以及读写操作时序-Particles as well as the DDR2 SDRAM initialization timing to read and write operations
Update : 2025-02-17 Size : 422kb Publisher : robert.wang
[VHDL-FPGA-Verilog] Xil3SD1800A_MIG_simplifiedUI_vlog_v92 DL : 0: verilog 实现的spartan 3A dsp start kit DDR2 SDRAM 控制器-verilog achieved spartan 3A dsp start kit DDR2 SDRAM controller
Update : 2025-02-17 Size : 887kb Publisher : ma yirong
[Documents] ddr2_sdram_controller DL : 0: 关于DDR2 SDRAM 控制器的相关论文资料-ddr2_sdram_controller
Update : 2025-02-17 Size : 5.41mb Publisher : 王颖伟
[VHDL-FPGA-Verilog] s3ask_ddr2 DL : 0: DDR2-400样例源代码，用于Xilinx Spartan 3A/3AN Starter Kit-DDR2-400 sample source code for Xilinx Spartan 3A/3AN Starter Kit
Update : 2025-02-17 Size : 2.49mb Publisher : Joe Zhu
[VHDL-FPGA-Verilog] mcb_read_write DL : 0: 赛灵思 DDR2 用户接口程序原创。希望对各位有用。-Xilinx DDR2 original user interface program. You want to be useful.
Update : 2025-02-17 Size : 2kb Publisher : wenchunhong
[VHDL-FPGA-Verilog] user_design DL : 0: spartan3a-ddr2 (16bits 333M)
Update : 2025-02-17 Size : 9.65mb Publisher : lhx
[VHDL-FPGA-Verilog] ddr2 DL : 0: ddr2的功能控制模块，3部分，只要调取就可以。-ddr2 control codes
Update : 2025-02-17 Size : 5kb Publisher : wenxin

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