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[VHDL-FPGA-Verilog] fir_sine

Description: This implementation is moderately memory efficient because it stores only the first Pi/2 radians of sine values. The second Pi/2 radians is a mirror image of the first in time and the second Pi radians is a mirror image in amplitude of the first Pi radians. Memory could be saved if the increments were recorded rather than each absolute value. Fewer bits per value would be needed, however, extra hardware would be needed for an adder.
Platform: | Size: 18432 | Author: jai | Hits:

[VHDL-FPGA-Verilog] UART

Description: 實作UART 介面 4 byte 傳送或 4 byte 接收開發環鏡 quartus 且附模擬檔-4 byte real interfaces for UART transmission or 4 byte receive loop mirror quartus and the development of simulation files attached
Platform: | Size: 1055744 | Author: 許大頭 | Hits:

[VHDL-FPGA-Verilog] XY2_100

Description: vhdl写的XY2100协议，该协议用于激光振镜(The XY2100 protocol written by VHDL, which is used for laser vibro mirror)
Platform: | Size: 1024 | Author: for er | Hits:

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[VHDL-FPGA-Verilog] fir_sine

[VHDL-FPGA-Verilog] UART

[VHDL-FPGA-Verilog] XY2_100

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