Search - VHDL s

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[Develop Tools] 可编程逻辑系统的VHDL设计技术_0 DL : 0: 可编程逻辑系统的VHDL设计技术,该本书首先对VHDL语言进行了阐述,然后用alter公司的产品进行举例!-programmable logic system VHDL design technology, the first book of VHDL expounded, and then alter the company's products, for example!
Update : 2008-10-13 Size : 10.51mb Publisher : 高操
[Embeded-SCM Develop] VHDL DL : 0: MARS-7128-S CPLD开发板VHDL 源码
Update : 2008-10-13 Size : 2.44mb Publisher : 史蒙克
[Other resource] Original-8051 Vhdl Model DL : 0: 這是Originl公司出的8051 VHDL source code.-It s a 8051 VHDL source code issued by Original.
Update : 2008-10-13 Size : 220kb Publisher : ㄚ福
[VHDL-FPGA-Verilog] R-S触发器 DL : 0: R-S触发器的vhdl语言描述
Update : 2011-04-26 Size : 341byte Publisher : 798291651@qq.com
[VHDL-FPGA-Verilog] Original-8051 Vhdl Model DL : 0: 這是Originl公司出的8051 VHDL source code.-It s a 8051 VHDL source code issued by Original.
Update : 2025-02-17 Size : 220kb Publisher : ㄚ福
[Books] 可编程逻辑系统的VHDL设计技术_0 DL : 0: 可编程逻辑系统的VHDL设计技术,该本书首先对VHDL语言进行了阐述,然后用alter公司的产品进行举例!-programmable logic system VHDL design technology, the first book of VHDL expounded, and then alter the company's products, for example!
Update : 2025-02-17 Size : 10.51mb Publisher : 高操
[VHDL-FPGA-Verilog] spi DL : 0: VHDL实现SPI功能源代码 -- The SPI bus is a 3 wire bus that in effect links a serial shift -- register between the "master" and the "slave". Typically both the -- master and slave have an 8 bit shift register so the combined -- register is 16 bits. When an SPI transfer takes place, the master and -- slave shift their shift registers 8 bits and thus exchange their 8 -- bit register values.-SPI realize the functional VHDL source code The SPI bus is a 3 wire bus that in effect links a serial shift register between the
Update : 2025-02-17 Size : 64kb Publisher : 阿飞
[VHDL-FPGA-Verilog] sin DL : 0: sin產生器，可以於VHDL產生sin之數值波形，進而輸出至dac做轉換-sin generator can produce sin in VHDL of the numerical waveform, and then make the conversion output to dac
Update : 2025-02-17 Size : 1.03mb Publisher : lin
[Data structs] vhdl DL : 0: 设计一个由甲、乙双方参赛，有裁判的3人乒乓球游戏机-Design of an A, B or both sides participating, there are 3 referee s table tennis game
Update : 2025-02-17 Size : 2kb Publisher : 李萧
[VHDL-FPGA-Verilog] SPI_collect DL : 0: 有关SPI的vhdl实现。包括SPI官方协议，几篇开发时用到的论文，附加了中文注释的SPI IPcore，还有一个经过简化的master mode的SPI实现的vhdl代码-Related to the VHDL SPI realize. Including SPI official agreement, when used to develop several theses, Chinese notes attached SPI IPcore, there is a simplified master mode the SPI realize the VHDL code
Update : 2025-02-17 Size : 1.27mb Publisher : danielmu
[assembly language] VHDLjianfaqi DL : 0: 这是一个利用MAX PULL 制作的VHDL的减法器的程序如果有需要仿真图的请叫站长联系我-This is a MAX PULL produced using VHDL s process of subtraction, if necessary simulation diagram contact me please call station
Update : 2025-02-17 Size : 1kb Publisher : 郭明磊
[VHDL-FPGA-Verilog] ref-ddr-sdram-vhdl DL : 0: 基于VHDL编写的DDR-SDRAM控制器的编程，目前是业界常用的RAM控制器-VHDL prepared based on the DDR-SDRAM controller programming, is currently the industry s commonly used RAM controller
Update : 2025-02-17 Size : 1007kb Publisher : wfs
[VHDL-FPGA-Verilog] spi_master_control DL : 0: VHDL SPI 控制器FPGA官网提供-VHDL SPI controller FPGA to provide official website
Update : 2025-02-17 Size : 655kb Publisher : lonely_vv
[VHDL-FPGA-Verilog] VHDL DL : 0: 双口RAM模块源代码（VHDL）,用于开发FPGA的双口RAM，可以直接下载到工程中使用。-Dual-port RAM module source code (VHDL), for the development of FPGA' s dual-port RAM, can be directly downloaded to the project use.
Update : 2025-02-17 Size : 1kb Publisher : wu
[Other] The-vhdl-gold-reference-guide DL : 0: 是一个公司内的资料，介绍了vhdl的常用语法结构，并说明了一些平时很少注意到的问题，是对vhdl学习的很好补充-A company' s information on the vhdl common grammatical structure, and explains some of the problems usually little attention is a good supplement to learn vhdl
Update : 2025-02-17 Size : 178kb Publisher : lideli5
[VHDL-FPGA-Verilog] VHDL-snake DL : 0: 一篇关于如何用VHDL做贪食蛇的游戏,内有源码.-An article on how to use VHDL to do Snake s game, there are source code inside .
Update : 2025-02-17 Size : 1.67mb Publisher : tony.wang
[VHDL-FPGA-Verilog] VHDL-based-design-of-SPI DL : 0: 基于VHDL的串行同步通信SPI设计本设计是用Quartus作为开发环境，以DE2板为硬件平台实现的SPI同步串行通讯。设计过程方便。根据接收和发送两个主要部分实现了SPI的基本功能。此外，该设计还实现了波特率发生器，数码管显示的功能。用DE2板实现具有电路简洁，开发周期短的优点。充分利用了EDA设计的优点。开发过程用了VHDL硬件描述语言进行描述，从底层设计，分模块进行，充分提高了设计者的数字逻辑设计的概念。-VHDL-based SPI serial synchronous communication design as the design is the use of Quartus development environment to DE2 board as the hardware platform of the SPI synchronous serial communication. Facilitate the design process. According to both send and receive SPI implements the main part of the basic functions. In addition, the design also implements the baud rate generator, digital display features. DE2 board to achieve a circuit with a simple, short development cycle advantages. Full use of the EDA design advantages. Development Process VHDL hardware description language used to describe the design from the ground, sub-module, to fully enhance the designer' s concept of digital logic design.
Update : 2025-02-17 Size : 50kb Publisher : 陈添
[VHDL-FPGA-Verilog] VHDL-(3) DL : 0: Introduction to the language - simple examples n VHDL’s model of a system
Update : 2025-02-17 Size : 65kb Publisher : Ali
[VHDL-FPGA-Verilog] The Designer's Guide to VHDL, Vol.3, Third Ed DL : 0: The Designer's Guide to VHDL, Vol.3, Third Ed.rar
Update : 2025-02-17 Size : 2.66mb Publisher : commando
[Software Engineering] Quartusii11_13192 DL : 0: 简单的一个硬件仿真语言，VHDL的quarter2的一个免费版软件，可以免费使用30天。(A simple hardware simulation language, a free version of VHDL's quarter2 software, can be used free for 30 days.)
Update : 2025-02-17 Size : 12kb Publisher : NOTO

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