Welcome！[Sign In] ！[Sign Up]！
Front-page it | Collect it | [中国-简体中文]
FAQ Fav
Location:
Search - VHDL time

Search list

[Other resource] VHDL编程教学示例

Description: 大家一定要看 哦 程序在与多看多练 我找了好久才找到呢-Oh, we must look at the procedures and see more and more training for a long time I find?
Platform: | Size: 1774793 | Author: 谭小果 | Hits:

[Other resource] VHDL-ysw

Description: 基于CPLD的棋类比赛计时时钟,第一个CNT60实现秒钟计时功能，第二个CNT60实现分钟的计时功能，CTT3完成两小时的计时功能。秒钟计时模块的进位端和开关K1相与提供分钟的计时模块使能，当秒种计时模块计时到59时向分种计时模块进位，同时自己清零。同理分种计时模块到59时向CTT3小时计时模块进位，到1小时59分59秒时，全部清零。同时，开关K1可以在两小时内暂停秒钟计时模块，分钟计时模块和小时计时模块。各模块的VHDL语言描述如下：-CPLD-based time clock chess competitions, a CNT60 achieve seconds timing, CNT60 second minute of time to achieve functional, CTT3 completion of the two-hour time function. Module seconds into time - and-switch K1 phase minutes for a time module can be enabled When seconds time to time module to the 59 minute time rounding module, reset themselves. Similarly minute time module to the 59-hour time CTT3 module rounding to 1 hour 59 minutes 59 seconds, reset all. Meanwhile, switches K1 can be suspended within two hours time module seconds, minutes and hours of time metering module module. The module VHDL is described as follows :
Platform: | Size: 2716 | Author: 杨仕伟 | Hits:

[Other resource] time

Description: vhdl语言编写秒表程序 内含每个模块的源程序
Platform: | Size: 235584 | Author: BILL | Hits:

[VHDL-FPGA-Verilog] 电子钟clock

Description: 用VHDL语言来实现一个电子时钟，可以调时间。小时，分，秒。可以下载到实验箱来运行验证。-use VHDL to achieve an electronic clock, the time can be set aside. Hours, minutes and seconds. Experiments can be downloaded to the box to run test.
Platform: | Size: 353280 | Author: 刘卫 | Hits:

[VHDL-FPGA-Verilog] 经典高速乘法器IP

Description: 乘法器是硬件设计中的很常见也很重要的一个模块，它的VHDL硬件实现很好的解决了软件编程中做乘法速度慢的问题，在实时高速系统应用中或DSP软核或数字信号处理硬件实现算法中，经常能使用到乘法器，所以经典的高速乘法器IP 很有参考价值-Multiplier is a common and important module in hardware designing.Its VHDL addresses the low speed of multiplication in software programming. Multiplier is often used in real-time high-speed system application , DSP soft core or hardware implementation of digital signal processing,so it is worthful to know classic high-speed multiplier IP
Platform: | Size: 309248 | Author: czy | Hits:

[Other] VHDL编程教学示例

Description: 大家一定要看 哦 程序在与多看多练 我找了好久才找到呢-Oh, we must look at the procedures and see more and more training for a long time I find?
Platform: | Size: 1774592 | Author: 谭小果 | Hits:

[Embeded-SCM Develop] VHDL

Description: VHDL数字钟 数字电子钟 此数字电子钟具有的功能包括： 1. 计时，时、分、秒显示； 2. 十二小时与二十四小时之间的转换； 3. 上下午显示； 4. 对时、分、秒的校时功能；-VHDL digital clock digital clock digital electronic clock with this function include: 1. Time, hours, minutes and seconds display 2. 12 hours and 24 hours between the conversion 3. On the afternoon show 4. hours, minutes and seconds of the school function
Platform: | Size: 3072 | Author: HJGJGHK | Hits:

[VHDL-FPGA-Verilog] VHDL

Description: 用VHDL实现数字频率计,1. 时基产生与测频时序控制电路模块2. 待测信号脉冲计数电路模块3.锁存与译码显示控制电路模块4.顶层电路模块. -Using VHDL digital frequency meter, 1. Time-base generation and frequency measurement timing control circuit module 2. Analyte signal pulse counting circuit module 3. Latch and decoding display control circuit module 4. Top-level circuit module.
Platform: | Size: 13312 | Author: 侯治强 | Hits:

[VHDL-FPGA-Verilog] time

Description: vhdl语言编写秒表程序 内含每个模块的源程序-VHDL language stopwatch program includes source code for each module
Platform: | Size: 235520 | Author: BILL | Hits:

[VHDL-FPGA-Verilog] vhdl

Description: 基于vhdl的数字时钟；24制，带有定时，闹钟等功能。-VHDL-based digital clock 24 system, with time, alarm clock functions.
Platform: | Size: 71680 | Author: jecky | Hits:

[VHDL-FPGA-Verilog] alarm-clock

Description: 基于vhdl的数字闹钟的设计。可实现计时、闹钟、调节时间功能。可以在FPGA上实现。-VHDL-based digital alarm clock design. Can achieve a time, alarm clock, adjust time function. FPGA implementation can be on.
Platform: | Size: 2048 | Author: tony | Hits:

[VHDL-FPGA-Verilog] Time

Description: 24小时时钟设计程序，含有时，分，秒的电路设计，基于VHDL语言，用Quartus 2程序实现。-24-hour clock design process, with hour, minute, second circuit design, based on the VHDL language, using Quartus 2 program.
Platform: | Size: 382976 | Author: 张苏昕 | Hits:

[Software Engineering] VHDL

Description: 在电子技术中，频率是最基本的参数之一，又与许多电参量的测量方案、测量结果都有十分密切的关系，因此频率的测量就显得更为重要。测量频率的方法有多种,其中电子计数器测量频率具有精度高、使用方便、测量迅速，以及便于实现测量过程自动化等优点，是频率测量的重要手段之一。在本次毕业设计中我们选择使用单片机来制作数字频率计，并在实际制作中采用了直接测频法。利用延时产生的时基门控信号来控制闸门，通过在单位时间内计数器记录下的脉冲个数计算出输入信号的频率，最终送入LCD中显示。这样制作出来的频率计不仅可以满足设计题目的参数要求，而且具有了单片机的稳定性和成熟性，且控制能力强，是一种低成本，高可靠的设计方案。-In electronic technology, the frequency is one of the most basic parameters, but also with a number of electrical parameters of the measurement program, the measurement results have a very close relationship between the frequency of measurement, therefore it is even more important. Measurement of the frequency of a number of means, electronic measurement of the frequency counter with high precision, easy to use, rapid measurement, and measurement is easy to realize the advantages of process automation is an important means of measuring the frequency of one. Graduates in this design we have chosen to make use of single-chip digital frequency meter, and used in the actual production of a direct frequency measurement method. Delay arising from the use of gated time-base signal to control the gate time in units of the pulse counter to record the number of calculated frequency of the input signal, and ultimately into the LCD display. This produced not only the frequency of the parameters to
Platform: | Size: 220160 | Author: 张林锋 | Hits:

[VHDL-FPGA-Verilog] VHDL

Description: 微波炉定时控制器的设计,已成功经过调试,并有相应的课程设计报告-Microwave oven controller design from time to time, after successfully testing and a corresponding report of the curriculum design
Platform: | Size: 187392 | Author: 林君霞 | Hits:

[VHDL-FPGA-Verilog] time

Description: 电子钟实现 包含数字跑表 万年历 设置三个闹钟 时间，日期调整-Clock to achieve with digital stopwatch calendar set three alarm time, date, adjust
Platform: | Size: 2048 | Author: 楚辰 | Hits:

[VHDL-FPGA-Verilog] VHDL

Description: （1）用VHDL语言编写程序，在EDA实验板上实现 （2）能正常计时。显示模式分为两种，即24小时制和12小时制。其中12小时制须显示上，下午（用指示灯显示）。时，分，秒都要显示。 （3）. 手动校准电路。用一个功能选择按钮选择较时，分功能，用另一个按钮调校对应的时和分的数值。 用VHDL语言编写程序，在EDA实验板上实现 （4） 整点报时。 （5）. 闹钟功能。 （6）．秒表功能。-(1) using VHDL language program, in the EDA experiments on-board implementation (2) to resume normal time. Display mode is divided into two kinds, namely, a 24-hour system and 12-hour clock. Including 12-hour clock to be displayed on the afternoon (with light display). Hours, minutes and seconds to be displayed. (3). Manual calibration circuit. With a select button to choose a more functional hours, minutes functions, with another button to adjust the corresponding time and sub-values. Using VHDL language programs, in the EDA experiments on-board implementation (4) The whole point timekeeping. (5). Alarm. (6). Stopwatch function.
Platform: | Size: 4096 | Author: malon | Hits:

[Software Engineering] vhdl-TAXI

Description: 随着EDA技术的发展及大规模可编程逻辑器件CPLD／FPGA的出现，电子系统的设计技术和工具发生了巨大的变化，通过EDA技术对CPLD／FPGA编程开发产品，不仅成本低、周期短、可靠性高，而且可随时在系统中修改其逻辑功能。本文利用VHDL语言设计出租车计费系统，使其实现汽车启动、停止、暂停时计费以及预置等功能，通过设置计数电路进行路费及路程的计数，通过设计数据转换电路将路费及路程的十进制数分离成四位十进制数表示，通过设计快速扫描电路显示车费及路费，突出了其作为硬件描述语言的良好的可读性的优点。通过MAX+PLUSⅡ软件编写、调试和优化源程序，下载到特定芯片（MAX系列的EPM 7128SLC8415）后，即可应用于实际的出租车计费系统中。-ith the development of EDA technologies and large-scale programmable logic device CPLD/FPGA emergence of electronic systems design techniques and tools has undergone tremendous changes, through the EDA technology CPLD/FPGA programming product development, not only low-cost, short lead time, high reliability, but also may at any time in the system to modify its logic function. In this paper, VHDL language design taxi billing system to achieve the car to start, stop, pause, time billing and preset functions, by setting the tolls and the distance counting circuit count, through the design of data conversion circuits and the journey will be toll separated into four decimal decimal number, said a quick scan through the design of the circuit shows fares and tolls, highlighting its position as a hardware description language, the advantages of good readability. Through the MAX+ PLUS Ⅱ software development, debugging and optimizing the source code, download to a specific chip (MAX series of EP
Platform: | Size: 269312 | Author: stella | Hits:

[VHDL-FPGA-Verilog] 32jie-vhdl-fir

Description: 32阶数字滤波器 没有时间来得及精简 不好意思了的说 呵呵 -32-order digital filter is not time enough time to streamline embarrassed to say Oh
Platform: | Size: 2048 | Author: 哈飞 | Hits:

[VHDL-FPGA-Verilog] VHDL-3BCD

Description: 3位BCD码的计数显示电路。BCD码计数电路从0计到9然后返回到0从新计数。3位BCD码计数器可以实现从0到999的十进制计数。要将计数过程用七段显示LED数码管显示出来，这里采用动态分时总线切换电路对数码管进行扫描，对数码管依次分时选中进行输出计数的个、十、百位的数据。-3 BCD code count display circuit. BCD code counting circuit count from 0 to 9 and then back to 0 from the new count. 3 BCD code counter can be achieved from 0 to 999 decimal count. Counting process with seven segment displays to LED digital tube displays, where dynamic time-sharing digital bus switch circuit to scan, followed by time-sharing of digital output selected for a count of ten, hundred bits of data.
Platform: | Size: 56320 | Author: will li | Hits:

[VHDL-FPGA-Verilog] FPGA-VHDL-Time-Constraints-example

Description: FPGA VHDL Time Constraints Example
Platform: | Size: 629760 | Author: mark | Hits:
« 12 3 4 5 6 7 8 9 10 ... 30 »

CodeBus www.codebus.net