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[File Operate] VHDL_clock DL : 0: 用VHDL能进行正常的时、分、秒计时功能、分别有6个数码管显示24小时、60分钟、60秒钟的计数器显示。-VHDL can be used for normal hours, minutes and seconds timing were six LED display 24 hours 60 minutes, 60 seconds showed that the counter.
Update : 2008-10-13 Size : 102.81kb Publisher : lianbin
[Other resource] vhdl_clock DL : 0: VHDL实现数字时钟，利用数码管和CPLD 设计的计数器实现一个数字时钟，可以显示小时，分钟，秒。程序主要要靠考虑十进制和六十进制计数器的编写。以上实验的程序都在源代码中有详细的注释-VHDL digital clock, the use of digital control and CPLD design to achieve a number of counter clock, show hours, minutes and seconds. The procedure depends on the metric system and consider six decimal counter preparation. The experimental procedure in the source code for a detailed Notes
Update : 2008-10-13 Size : 317.33kb Publisher : 赵海东
[Other resource] VHDL_clock DL : 0: 数字钟实现时、分、秒的显示和定时闹铃、整点报时等功能。
Update : 2008-10-13 Size : 9.19kb Publisher : 吴称光
[File Format] VHDL_clock DL : 0: 用VHDL能进行正常的时、分、秒计时功能、分别有6个数码管显示24小时、60分钟、60秒钟的计数器显示。-VHDL can be used for normal hours, minutes and seconds timing were six LED display 24 hours 60 minutes, 60 seconds showed that the counter.
Update : 2025-02-17 Size : 103kb Publisher : lianbin
[VHDL-FPGA-Verilog] vhdl_clock DL : 0: VHDL实现数字时钟，利用数码管和CPLD 设计的计数器实现一个数字时钟，可以显示小时，分钟，秒。程序主要要靠考虑十进制和六十进制计数器的编写。以上实验的程序都在源代码中有详细的注释-VHDL digital clock, the use of digital control and CPLD design to achieve a number of counter clock, show hours, minutes and seconds. The procedure depends on the metric system and consider six decimal counter preparation. The experimental procedure in the source code for a detailed Notes
Update : 2025-02-17 Size : 317kb Publisher : 赵海东
[source in ebook] VHDL_clock DL : 0: 数字钟实现时、分、秒的显示和定时闹铃、整点报时等功能。-Realize digital clock hour, minute, second display and timing alarm, the whole point timekeeping functions.
Update : 2025-02-17 Size : 9kb Publisher : 吴称光
[VHDL-FPGA-Verilog] vhdl_clock DL : 0: VHDL数字钟设计程序设计要求基本要求： 1、24小时计数显示； 2、具有校时功能（时，分）；附加要求： 1、实现闹钟功能（定时，闹响）；-VHDL digital clock design process design requirements for the basic requirements: 1,24 hours count display 2, with a school function (hours, minutes) additional requirements: 1, the realization of an alarm clock function (timing, downtown ring)
Update : 2025-02-17 Size : 7kb Publisher : 孙超
[VHDL-FPGA-Verilog] VHDL_clock DL : 0: 用VHDL写的数字电子钟的实例，采用的是altera的FPGA芯片-VHDL examples of digital electronic clock
Update : 2025-02-17 Size : 6kb Publisher : zhangwei
[VHDL-FPGA-Verilog] VHDL_clock DL : 0: VHDL数字钟设计程序设计要求基本要求： 1、24小时计数显示； 2、具有校时功能（时，分）；附加要求： 1、实现闹钟功能（定时，闹响）；--VHDL design process digital clock design basic requirements: 1.24 hours count display 2, when a school function (hour, minute) additional requirements: 1, to achieve alarm (time, alarm sound) -
Update : 2025-02-17 Size : 70kb Publisher : 苹果熊
[VHDL-FPGA-Verilog] VHDL_clock DL : 0: 关于电子数字钟得FPGA实现，上传来分享一下-Electronic digital clock was on the FPGA, upload to share with you
Update : 2025-02-17 Size : 2.63mb Publisher : 甘超
[VHDL-FPGA-Verilog] VHDL_clock DL : 0: VHDL电子钟,课程设计，时间可调，有闹钟，大小月，闰年，整点报时-a clock which is write in VHDL language
Update : 2025-02-17 Size : 39kb Publisher : 王宇
[VHDL-FPGA-Verilog] VHDL_clock DL : 0: 运用VHDL写的时钟控制程序，状态机，时钟分频，频率变换。-VHDL clock
Update : 2025-02-17 Size : 11.61mb Publisher : YH