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Description: 中国科学院计算所李晓维研究员的VLSI测试与可测试性设计讲义
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Size: 3555850 |
Author: 杨涛 |
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Description: 中科院研究生院VLSI测试课程课件，VLSI TEST PRINCIPLES AND ARCHITECTURES
Design for Testability，搞好测试必看。
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Size: 5425369 |
Author: xzy |
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Description: 中国科学院计算所李晓维研究员的VLSI测试与可测试性设计讲义-Calculated by the Chinese Academy of Sciences researcher Li Xiaowei of VLSI testing and design for testability notes
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Size: 3556352 |
Author: 杨涛 |
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Description: 中科院研究生院VLSI测试课程课件，VLSI TEST PRINCIPLES AND ARCHITECTURES
Design for Testability，搞好测试必看。-Chinese Academy of Sciences, Graduate School of VLSI test Courseware, VLSI TEST PRINCIPLES AND ARCHITECTURESDesign for Testability, do a good job in testing a must-see.
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Size: 5425152 |
Author: xzy |
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Description: VLSI Test Principles and Architectures Design for Testability..... very nice pdf
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Size: 5026816 |
Author: marry |
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Description: 基于stack-at fault的超大规模数字集成电路自动测试向量生成算法（ATPG）。输入.bench格式，输出测试向量。-Automatic test pattern generation (ATPG) algorithm for VLSI circuits
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Size: 237568 |
Author: Roger |
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Description: c program to levelise a combinational vlsi circuits in test pattern generation. it will work for iscas 85 benchmark circuits
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Size: 4096 |
Author: sujitha |
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Description: about adavance self genersated test sequnce in VLSI
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Size: 310272 |
Author: ashu |
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Description: VLSI Test slides from "VLSI Test arch" book.
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Size: 209920 |
Author: DIG |
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Description: Slides from book "VLSI Test principles"
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Size: 441344 |
Author: DIG |
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Description: Slides from "VLSI test" book.
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Size: 734208 |
Author: DIG |
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Description: Slides from "VLSI test" book.
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Size: 535552 |
Author: DIG |
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Description: Slides from "VLSI Test arch" book
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Size: 675840 |
Author: DIG |
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Description: introduction to vlsi testing
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Size: 475136 |
Author: sathya |
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Description: Ruby LFSR 模拟程序。 可以自动生成任意位数的VLSI test pattern用于VLSI TEST. 含有两种lfsr,等概率LFSR和加权LFSR.-LFSR simulator based on ruby language.
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Size: 1024 |
Author: Yuheng |
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Description: 集成电路测试软件入门资料,要满20个字~~POI-VLSI test go into door Ziliao
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Size: 1590272 |
Author: 蔡宇杰 |
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Description: VLSI Design and Test.pdf-Abstract. Significant speed degradation is one of the severest issues encountered in low-voltage Static Random Access Memory (SRAM) operation. In
addition, Sense Amplifier (SA) stability deterioration is another problem in
low-voltage operation. These phenomena occur because the random transistor
variation becomes larger as the process scaling progresses.
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Size: 12190720 |
Author: chenwei |
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Description: Low-Power Programmable PRPG With Test
Compression Capabilities
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Size: 2897920 |
Author: ashok chakravarthy |
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Description: A new low-power (LP) scan-based built-in selftest
(BIST) technique is proposed based on weighted pseudorandom
test pattern generation and reseeding. A new LP scan
architecture is proposed, which supports both pseudorandom
testing and deterministic BIST. During the pseudorandom testing
phase, an LP weighted random test pattern generation scheme
is proposed by disabling a part of scan chains.
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Size: 1568768 |
Author: Maddy619
|
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Description: VLSI test slides - VLSI TEst archiecture book
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Size: 633856 |
Author: dig_des |
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