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[Other resource] cache

Description: 原创VERILOG HDL 实现CACHE的操作，有需要请下载-original verilog HDL achieve CACHE operation, the need to download
Platform: | Size: 4850 | Author: MingCheng | Hits:

[VHDL-FPGA-Verilog] ARM9_instruction_cache_verilogCodes

Description: Arm9指令Cache缓存模块的verilog代码，对一些做ARM硬件开发的朋友有参考价值。-Arm9 Instruction Cache Cache Module Verilog code, do some of the hardware development of the ARM friends reference value.
Platform: | Size: 3072 | Author: 杨力 | Hits:

[VHDL-FPGA-Verilog] riscpu

Description: 一个32位微处理器的verilog实现源代脉,采用5级流水线和cache技术.-a 32 Microprocessor verilog achieve pulse generation sources, used five lines and cache technology.
Platform: | Size: 152576 | Author: 大为 | Hits:

[VHDL-FPGA-Verilog] deinterlace

Description: Xilinx提供的一种利用线缓存进行插值的隔行变逐行程序，比普通算法效果有很大改进。-Xilinx to provide a linear interpolation for the cache interlaced progressive change procedures, than ordinary algorithm results are greatly improved.
Platform: | Size: 99328 | Author: cloud | Hits:

[VHDL-FPGA-Verilog] cache

Description: 原创VERILOG HDL 实现CACHE的操作，有需要请下载-original verilog HDL achieve CACHE operation, the need to download
Platform: | Size: 4096 | Author: MingCheng | Hits:

[VHDL-FPGA-Verilog] riscmcu

Description: 精简CPU设计，需要的可以下来看看,是VERILOG语言写的-streamlined CPU design, the need to be down look at the language is written in verilog
Platform: | Size: 79872 | Author: 磊 | Hits:

[VHDL-FPGA-Verilog] uartverlog

Description: 占用资源少的verilog HDL uart接口；采用固定波特率115200，可以修改程序中的分频来修改波特率，模式为1个启始位，8位数据位，1个停止位；带1字节缓存；当缓存空时输出空信号-Occupy fewer resources verilog HDL uart interface adopted a fixed baud rate of 115200, can modify the procedure to modify the baud rate frequency, the model of a start bit, 8 data bits, 1 stop bit with one word section of the cache when the cache empty space-time output signal
Platform: | Size: 2048 | Author: 张诚 | Hits:

[Other] videocap

Description: 视频采集控制缓存SRAM读写，对做视频采集有很好的参考。-Video capture control of the cache SRAM read and write, and to do video capture a very good reference.
Platform: | Size: 8192 | Author: 刘留 | Hits:

[VHDL-FPGA-Verilog] pingpang

Description: 实现乒乓缓存，用verilog语言编写！-Realize cache ping-pong, using Verilog language!
Platform: | Size: 165888 | Author: zhl | Hits:

[VHDL-FPGA-Verilog] mipsCPU

Description: MIPS CPU tested in Icarus Verilog
Platform: | Size: 20480 | Author: imromeo | Hits:

[VHDL-FPGA-Verilog] FIFO_8_8

Description: FIFO先进先出队列，一种缓存、或一种管道、设备、接口（Verilog HDL程序,内附说明）-FIFO FIFO queue, a cache, or a pipeline, equipment, Interface (Verilog HDL program, containing a note)
Platform: | Size: 5120 | Author: 镜子 | Hits:

[VHDL-FPGA-Verilog] mips1

Description: Verilog MIPS design. I found it somewhere on Internet and it is working :-Verilog MIPS design. I found it somewhere on Internet and it is working :))))
Platform: | Size: 18432 | Author: Asparuh Grigorov | Hits:

[VHDL-FPGA-Verilog] 5_lined_cpu

Description: 简单5级流水线CPU的verilog逻辑设计-Simple line 5 of the CPU logic design verilog
Platform: | Size: 1024 | Author: 张健 | Hits:

[VHDL-FPGA-Verilog] dCACHE

Description: Vhdl写的数据cache,根据Verilog程序改编-Vhdl write data cache
Platform: | Size: 10240 | Author: 赵元杰 | Hits:

[VHDL-FPGA-Verilog] iCACHE

Description: 用VHDL写的数据cache，基于Verilog版本改编过来-To use VHDL to write the data cache, based on the Verilog version of the adaptation over
Platform: | Size: 7168 | Author: 赵元杰 | Hits:

[VHDL-FPGA-Verilog] PIPE_LINING_CPU_TEAM_24

Description: 采用Quatus II编译环境，使用Verilog HDL语言编写实现了五段流水线CPU。 能够完成以下二十二条指令（均不考虑虚拟地址和Cache，并且默认为小端方式）： add rd,rs,rt addu rd,rs,rt addi rt,rs,imm addiu rt,rs,imm sub rd,rs,rt subu rd,rs,rt nor rd,rs,rt xori rt,rs,imm clo rd,rs clz rd,rs slt rd,rs,rt sltu rd,rs,rt slti rt,rs,imm sltiu rt,rs,imm sllv rd,rt,rs sra rd,rt,shamt blez rs,imm j target lwl rt,offset(base) lwl rt,offset(base) lw rt,imm(rs) sw rt,imm(rs) 在本设计中，采取非常良好的模块化编程风格，共分十三个主要模块PIPE_LINING_CPU_TEAM_24.v为顶层实体文件，对应为PIPE_LINING_CPU_TEAM_24模块作为顶层实体模块，如下： ifetch.v、regdec.v、exec.v、mem.v、wr.v分别实现五个流水段； cpuctr.v用于产生CPU控制信号； ALU.v用于对操作数进行相应指令的运算并输出结果； DM.v数据存储器 IM.v指令存储器 datareg.v数据寄存器堆 extender.v位扩展 yiwei_32bits.v 实现32位四种移位方式的移位器 在顶层实体中，调用ifetch.v、regdec.v、exec.v、mem.v、wr.v这五个模块就实现了流水线CPU。顶层模块的结构清晰明了。对于学习verilog编程非常有用- Quatus II compiled by the environment, using Verilog HDL language to achieve a five-stage pipeline CPU. To complete the following 22 commands (not considering the virtual address and Cache, and the default mode for the small end): add rd, rs, rt addu rd, rs, rt addi rt, rs, imm addiu rt, rs, imm sub rd, rs, rt subu rd, rs, rt nor rd, rs, rt xori rt, rs, imm clo rd, rs clz rd, rs slt rd, rs, rt sltu rd, rs, rt slti rt, rs, imm sltiu rt, rs, imm sllv rd, rt, rs sra rd, rt, shamt blez rs, imm j target lwl rt, offset (base) lwl rt, offset (base) lw rt, imm (rs) sw rt, imm (rs) In this design, take a very good modular programming style, is divided into 13 main modules PIPE_LINING_CPU_TEAM_24.v for the top-level entity file, the corresponding module as a top-level entity for the PIPE_LINING_CPU_TEAM_24 modules, as follows: ifetch.v, regdec.v, exec.v, mem.v, wr.v water were to achieve the five paragraph cpuctr.v used to generate CPU control signal ALU.v accordingly
Platform: | Size: 4946944 | Author: 石 | Hits:

[VHDL-FPGA-Verilog] PipelineCPU

Description: 用Verilog实现一个简单的流水线CPU，并运行一个Quicksort程序。这是Berkley，eecs系的计算机系统结构课程实验的实验三。-This file is written in Verilog to achieve a simple pipeline CPU, which can run a Quicksort program.
Platform: | Size: 28672 | Author: Matgek | Hits:

[VHDL-FPGA-Verilog] cache

Description: 缓存器 cache verilog 欢迎下载偶-cache verilog
Platform: | Size: 5120 | Author: yzhang | Hits:

[VHDL-FPGA-Verilog] ping_pong_buffer

Description: 用寄存器来实现乒乓缓存(Verilog HDL)-Ping-pong with the register to achieve cache (Verilog HDL)
Platform: | Size: 36864 | Author: 小强 | Hits:

[VHDL-FPGA-Verilog] code-water-no-cache

Description: 5级流水无cache的cpu代码，基于verilog，串行，两级流水-cpu code with no water nor cache
Platform: | Size: 12288 | Author: Victor | Hits:
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