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[VHDL-FPGA-Verilog] I2Cslave

Description: i2c slave,这个是I2CBUS接收端的源代码，由VERILOG写成，经过综合和调试-i2c slave, this is the receiving end I2CBUS source code, from VERILOG languages, through integrated and debug
Platform: | Size: 1024 | Author: Xiaoyang Wang | Hits:

[VHDL-FPGA-Verilog] dynamic_display

Description: 4 digital LED dynamic display的Verilog HDL源代码，它能动态的显示4位数，为FPGA 的DEBUG 提供便利，非常经典，简单易懂，并且经过了Modelsim/ISE/FPGA(XC3S250ETQ144)验证和实现，好的行为模型就应该大家分享。-4 digital LED dynamic display of the Verilog HDL source code, it can dynamically display 4-digit for the FPGA to facilitate the DEBUG, very classic, easy-to-read, and after Modelsim/ISE/FPGA (XC3S250ETQ144) authentication and realize, good The behavior model should be shared.
Platform: | Size: 257024 | Author: name | Hits:

[Multimedia program] video_compression_systems.tar

Description: 视频、图像压缩代码，内附使用说明，建立相应工程后，将Verilog代码ADD之后就可以编译调试，对于学习图像压缩或熟悉FPGA调试环境的人员会有一定的帮助-Video, image compression code, containing instructions to establish the corresponding work will Verilog code can be compiled after ADD debugging, for learning image compression, or are familiar with FPGA debug environment will help staff
Platform: | Size: 186368 | Author: 王弋妹 | Hits:

[Communication] 16pam

Description: 用VERILOG语言实现16QAM的数字调制的程序，已经在ISE10.1版本中调试通过-Using Verilog language realize 16QAM digital modulation procedures are in the debug version ISE10.1 through
Platform: | Size: 7684096 | Author: 王莉 | Hits:

[Other] Verilog_PS2_RS232

Description: 实现PS/2接口与RS-232接口的数据传输， PS/2键盘上按下按键，可以通过RS-232自动传送到主机的串口调试终端上，并在数据接收区显示接收到的字符。 串口调试终端的设置：波特率115200，一个停止位，无校验位。 -The realization of PS/2 interface with RS-232 data interface, PS/2 keyboard to press the button, through RS-232 automatic transmission to the host serial debug terminal and reception area in the data display received characters. Serial debug terminal settings: 115200 baud rate, one stop bit, no parity bit.
Platform: | Size: 1607680 | Author: chalin tong | Hits:

[VHDL-FPGA-Verilog] fifo

Description: 异步fifo，用Verilog编写，包含testbench，已经通过modelsim调试，内含文档和波形图-Asynchronous fifo, to prepare to use Verilog, including testbench, debug modelsim has passed, including documents and wave
Platform: | Size: 40960 | Author: iechshy1985 | Hits:

[VHDL-FPGA-Verilog] SDRAMController

Description: xilinx公司SDRAM的参考设计,调试成功-xilinx' s SDRAM reference design, debug successful
Platform: | Size: 128000 | Author: 陈俊 | Hits:

[VHDL-FPGA-Verilog] jtag

Description: verilog jtag源码及原理，还有debug模块。边界扫描等-verilog jtag source and principle, as well as debug module. Boundary-Scan, etc.
Platform: | Size: 10044416 | Author: jack | Hits:

[VHDL-FPGA-Verilog] x3cs400_uart

Description: 基于X3cS400的串口通讯程序，开发环境ISE7.0，使用verilog编写。可以使用串口调试助手在pc机上查看字符。-UART communication program based on X3CS400 FPGA， develop enviroment： ISE7.0，completed by verilog。 The result could be seen on the Uart debug assitant.
Platform: | Size: 569344 | Author: lingfeng | Hits:

[VHDL-FPGA-Verilog] 255

Description: 全数字锁相环的Verilog源代码，经过仿真调试-All-digital PLL Verilog source code, through the simulation to debug
Platform: | Size: 154624 | Author: 张文 | Hits:

[VHDL-FPGA-Verilog] FPGA

Description: FPGA应用开发入门与典型实例 代码 FPGA（现场可编程逻辑器件）以其体积小、功耗低、稳定性高等优点被广泛应用于各类电子产品的设计中。本书全面讲解了FPGA系统设计的背景知识、硬件电路设计，硬件描述语言Verilog HDL的基本语法和常用语句，FPGA的开发工具软件的使用，基于FPGA的软核嵌入式系统，FPGA设计的基本原则、技巧、IP核， FPGA在接口设计领域的典型应用，FPGA＋DSP的系统设计与调试，以及数字变焦系统和PCI数据采集系统这两个完整的系统设计案例。 -FPGA Application Development and Typical examples of code for FPGA (field programmable logic device) for its small size, low power consumption, high stability, the advantages are widely used in the design of electronic products. This book comprehensively explained the background FPGA system design, hardware design, hardware description language Verilog HDL syntax and basic common statement, FPGA use of the software development tools, FPGA-based soft-core embedded systems, FPGA design of the basic principles , skills, IP core, FPGA interface design field in a typical application, FPGA+ DSP system design and debug, and digital zoom systems and PCI data acquisition system design of two cases of complete system.
Platform: | Size: 10980352 | Author: 海到无涯 | Hits:

[VHDL-FPGA-Verilog] div

Description: VERILOG除法器，已经调试好。大家可以参照学习.-sub-divided function,I have debug it right.It is helpful to you
Platform: | Size: 129024 | Author: xiaowang | Hits:

[VHDL-FPGA-Verilog] moore

Description: moore状态机实验verilog代码，我已经调试好。希望供大家学习使用。-moore state machine code of verilog HDL.Debug it right.
Platform: | Size: 295936 | Author: xiaowang | Hits:

[VHDL-FPGA-Verilog] LIP1501CORE_dbg_interface

Description: Verilog Debug interface code
Platform: | Size: 199680 | Author: jc | Hits:

[VHDL-FPGA-Verilog] ddsfinal1

Description: verilog语言实现的dds代码，并行通信，生成四种波形，大赛编写的代码，modelsim仿真-verilog language dds code,modelsim debug
Platform: | Size: 1137664 | Author: 杨天 | Hits:

[Com Port] FPGA-RS232-verilog

Description: fpga上的串口驱动程序，包括接收主机来的数据（deserial）和发送由FPGA产生的数据(serial).该程序的调试需要借助串口调试助手-serial port driver on the fpga, including the receiving host to the data (deserial) and send the data generated by the FPGA (serial) to pc. The program needs the serial debug debugging assistant
Platform: | Size: 500736 | Author: yvaine | Hits:

[VHDL-FPGA-Verilog] Verilog

Description: 基于Quartus II 9.0 (32-Bit)的Verilog语言时钟程序，五个独立按键分别可调十分秒的加减和确定，此程序通过硬件调试成功。-Based on Quartus II 9.0 (32-Bit) of the Verilog language, clock, five independent second key addition and subtraction, respectively, is adjustable and determined the success of this program by hardware debug.
Platform: | Size: 4301824 | Author: 曾斌 | Hits:

[Other] verilog_pwm

Description: 用verilog调试成功的一个pwm波形，可以参考一下哈！-A pwm waveform verilog debug reference!
Platform: | Size: 483328 | Author: 周向阳 | Hits:

[VHDL-FPGA-Verilog] AD9229

Description: AD9229 verilog调试（K7平台）-AD9229 verilog debug (K7 platform)
Platform: | Size: 97280 | Author: 2012attitude | Hits:

[VHDL-FPGA-Verilog] ARM_SOC

Description: ARM最小系统，vivado或ISE综合后下载至FPGA板子上可以做ARM用，包含连接在AHB总线上的RAM和ROM，ARM内核引出JTAG接口，可以连接调试器用keil-MDK进行调试！(ARM minimum system, vivado or ISE integrated download to the FPGA board can be used as ARM, including the RAM and ROM connected to the AHB bus, the ARM kernel leads to the JTAG interface, can connect the debugger to debug with keil-MDK!)
Platform: | Size: 688128 | Author: ldz13180882132 | Hits:
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