Search - Verilog FM

[Other resource] dds_ise7.1_su

Description: 用Verilog语言实现信号发生器，包括AM，FM,PM，ASK,PSK,FSK调制。-using Verilog language signal generator, including AM, FM, PM, ASK, PSK, FSK modulation.
Platform: | Size: 5426 | Author: lee | Hits:

[VHDL-FPGA-Verilog] simple_fm_receiver.tar

Description: FM收音机的解码及控制器VHDL语言实现，Xilinx提供的．别谢我．-FM radio decoder and controller VHDL, Xilinx provide. I thank other.
Platform: | Size: 70656 | Author: 喻袁洲 | Hits:

[VHDL-FPGA-Verilog] dds_ise7.1_su

Description: 用Verilog语言实现信号发生器，包括AM，FM,PM，ASK,PSK,FSK调制。-using Verilog language signal generator, including AM, FM, PM, ASK, PSK, FSK modulation.
Platform: | Size: 5120 | Author: lee | Hits:

[SCM] DDS

Description: 基于ｆｐｇａ，采用ｑｕａｒｔｕｓ２的ＤＤＳ信号发生器，采用高速ＤＡＣ９０８为数模芯片，并可通过５１单片机送入调制信号进行ＦＭ调制-Based on the fpga, the use of the DDS signal generator quartus2 using DAC908 number of high-speed chip module, and passed into 51 single-chip FM modulation signal modulation
Platform: | Size: 2745344 | Author: 张新 | Hits:

[VHDL-FPGA-Verilog] vhld_fpga_box

Description: Verilog 编写的波形发生器，可发生正弦波，三角波，方波，可以调频-Prepared Verilog waveform generator, can occur sine, triangle wave, square wave, you can FM
Platform: | Size: 267264 | Author: ivan | Hits:

[VHDL-FPGA-Verilog] dds_final

Description: 使用Verilog HDL语言实现的一个DDS，可以发生0-10Mhz正弦波、方波、三角波，频率步进可调，FM调制、AM调制，调制度可调。DA芯片为8位并行，160MHz-Using the Verilog HDL language implementation of a DDS, can occur 0-10Mhz sine, square, triangle wave, frequency step tunable, FM modulation, AM modulation, adjustable modulation. DA-chip 8-bit parallel, 160MHz
Platform: | Size: 1638400 | Author: nostalgia | Hits:

[Algorithm] cordic_atan

Description: 用verilog语言实现计算反正切函数，在软件无线电中解调PM/FM中使用的尤为频繁。上传的压缩包是modelsim工程，基于6.5c,里边包含一个完整的PM波产生以及解调过程的matlab文件仿真，并取其中间的I和Q支路做为verilog文件的输入，并将其借条输出与MATLAB实际解调输出作比较。鉴相器的设计基于CORDIC算法，其精度取决于迭代的深度。由于工程实际运用只需要解调出atan值，并不需要绝对的值，所以并没有给予加权，需要的同学可以自己加上。-Calculated using verilog language arc tangent function, the software radio demodulation PM/FM is particularly used frequently. From the archive is modelsim project, based on 6.5c, inside the PM contains a complete demodulation process of wave generation and simulation matlab file, and whichever is the middle of the I and Q branch verilog file as input, and its IOU demodulated output and actual output of MATLAB for comparison. Phase detector design is based on CORDIC algorithm, its accuracy depends on the iteration depth. As the practical application of engineering demodulated atan value only and does not need absolute value, and there is no weight given to the need of the students can add their own.
Platform: | Size: 79872 | Author: Jorge | Hits:

[VHDL-FPGA-Verilog] DDS

Description: 能在DDS中用Verilog HDL语言实现FM,AM,FSK,ASK,PSK，结合可编程器件FGPA等等就能实现这些功能 -DDS can be used in Verilog HDL language FM, AM, FSK, ASK, PSK, etc. FGPA programmable devices can be combined to achieve these functions
Platform: | Size: 6281216 | Author: 王凡 | Hits:

[Other] all_digital_communication

Description: verilog 数字通信的接收机，FM的QAM的也涉及-verilog ALL digital communication
Platform: | Size: 5031936 | Author: 陈俊杰 | Hits:

[source in ebook] tiaopin

Description: 此程序用ISE的verilog编写，主要用于调频通信系统中，经过仿真，正确，希望对大家有帮助-This program was written with the ISE verilog mainly used for FM communications systems, simulation, and right, and I hope for all of us to help
Platform: | Size: 1469440 | Author: 牧童 | Hits:

[VHDL-FPGA-Verilog] DDS

Description: Verilog实现DDS线性调频，Verilog实现DDS线性调频-Verilog implementation of DDS linear FM，Verilog implementation of DDS linear FM
Platform: | Size: 1024 | Author: youyou | Hits:

[VHDL-FPGA-Verilog] FM_T

Description: 一个简单的FM调制模块，FM发射，用Verilog编写，基于Xilinx SPARTAN6 XC6LX9开发-A simple FM modulation modules for FM transmitter, using Verilog prepared, based on XILINX SPARTAN6 XC6LX9 Development
Platform: | Size: 1205248 | Author: 郭永峰 | Hits:

[VHDL-FPGA-Verilog] pll

Description: 一个基于FPGA的载波同步环的设计，开发语言Verilog，开发工具ISE 14.7，可用于FM接收机中，典型SDR项目-An FPGA-based carrier synchronization loop design, development language Verilog, development tools ISE 14.7, FM receivers can be used, typically SDR project
Platform: | Size: 2273280 | Author: 郭永峰 | Hits:

[VHDL-FPGA-Verilog] ex1_clkdiv

Description: 这个实验可以说是verilog入门最基础的实验了，我们不做太多的理论分析，实践是硬道理。当CPLD的I/O（ FM）为低电平时，三极管导通，蜂鸣器发声。-This experiment can be said to be the most basic experiments verilog entry, and we do not do a lot of theoretical analysis, practice is the last word. When the CPLD' s I/O (FM) is low, the transistor is turned on, the buzzer sounds.
Platform: | Size: 503808 | Author: 贺亚晨 | Hits:

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[Other resource] dds_ise7.1_su

[VHDL-FPGA-Verilog] simple_fm_receiver.tar

[VHDL-FPGA-Verilog] dds_ise7.1_su

[SCM] DDS

[VHDL-FPGA-Verilog] vhld_fpga_box

[VHDL-FPGA-Verilog] dds_final

[Algorithm] cordic_atan

[VHDL-FPGA-Verilog] DDS

[Other] all_digital_communication

[source in ebook] tiaopin

[VHDL-FPGA-Verilog] DDS

[VHDL-FPGA-Verilog] FM_T

[VHDL-FPGA-Verilog] pll

[VHDL-FPGA-Verilog] ex1_clkdiv

[VHDL-FPGA-Verilog] fm0_encode

[VHDL-FPGA-Verilog] FPGA_FM

[VHDL-FPGA-Verilog] FM

[VHDL-FPGA-Verilog] Comprehensive_FM_IP

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