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[VHDL-FPGA-Verilog] simple_fm_receiver.tar

Description: FM收音机的解码及控制器VHDL语言实现，Xilinx提供的．别谢我．-FM radio decoder and controller VHDL, Xilinx provide. I thank other.
Platform: | Size: 70656 | Author: 喻袁洲 | Hits:

[Other] hbf

Description: 在软件无线电中半带滤波器的设计与实现，半带滤波器实现的是2的幂次的抽取或插值。 -In software radio half-band filter design and realization of half-band filter is the realization of 2-power extraction or interpolation.
Platform: | Size: 246784 | Author: 岑楠 | Hits:

[VHDL-FPGA-Verilog] cordic

Description: verilog源代码，用于软件无线电中，cordic函数-Verilog source code for software radio, cordic function
Platform: | Size: 2048 | Author: 史兵 | Hits:

[Other] code_for_wireless_communication

Description: 包含软件无线电、dds、滤波器设计、数字调制解调等常用无线通信设计的matlab\verilog源码-Contains software radio, dds, filter design, digital modulation and demodulation of wireless communication, such as commonly used design matlabverilog source
Platform: | Size: 197632 | Author: 李大鹏 | Hits:

[Program doc] ddc

Description: 介绍了一种基于软件无线电思想的频分多址中频数字化接收机系统设计方案。它采用Altera公司的FPGA构成核 心单元,通过不同的软件配置实现对三路频分多址信号的解调。 -Introduce a software-based radio thinking FDMA digital IF receiver system design. It uses Altera s FPGA constitute the core unit, through different software configuration for the three-way realize FDMA signal demodulation.
Platform: | Size: 816128 | Author: 可难 | Hits:

[Books] CMMB-protocol

Description: CMMB-GYT220.1(2006：传输部分，广播通信的帧结构、信道编码与调制).pdf CMMB-GYT220.2(2006：复用部分，各种音视频，数据，ESG的复用方式).pdf CMMB-GYT220.3(2007：业务部分，电子业务指南（ESG）的编辑和使用).pdf CMMB-GYT220.4(2007：紧急广播).pdf CMMB-GYT220.5(2008：数据广播，各种数据内容的打包封装格式).pdf CMMB-GYT220.6(2008：条件接收，付费节目内容的控制方式).pdf CMMB-GYT220.7(2008：接收终端，各种手机，PMP，电视棒，车载机的接收规范 ).pdf-CMMB-GYT220.1 (2006: transmission parts, radio communications frame structure, channel coding and modulation). Pdf CMMB-GYT220.2 (2006: reuse of a variety of audio and video, data, ESG Reuse way). pdf CMMB-GYT220.3 (2007: the business part of e-business guide (ESG) and the use of the editorial). pdf CMMB-GYT220.4 (2007: emergency radio). pdf CMMB-GYT220.5 (2008: data broadcasting, the types of data content of the package package format). pdf CMMB-GYT220.6 (2008: conditional access, pay-content control). pdf CMMB-GYT220.7 (2008: the receiving end, all kinds of mobile phones, PMP, TV rods, automotive machine receiving norms). pdf
Platform: | Size: 3057664 | Author: 少 | Hits:

[Software Engineering] ddc

Description: 随着数模转换器硬件的快速发展和DSP处理能力及处理速度的逐步提高，软件无线电技术在商用和军用无线电通信领域也越来越显示出其强大的吸引力。本文研究的高速中频采样和数字下变频技术是目前蓬勃发展的软件无线电领域的两项关键技术。-As advances in technology provide increasingly faster and less expensive digital hardware, more of the traditionally analog functions of a radio receiver will be replaced with software or digital hardware. The software radio has show its fascinating functions in both commercial and military wireless communication. The high speed and high resolution analog-to-digital converter and digital down-converter which are researched in this thesis are two of the key technologies in the field of software radio that is vigorously developing recently.
Platform: | Size: 2652160 | Author: zc | Hits:

[Books] fir

Description: 本文以软件无线电为指导，提出基于CORDIC算法利用FPGA平台数字下变频器设计方案。首先分析下变频器的结构；然后采用模块化设计思想，将数字下变 频的功能模块包括数字控制振荡器、CIC抽取滤波、HBF抽取滤波器、FIR低通滤波器进行分析和FPGA的设计；最后在 MATLAB/DSPBuilder下硬件仿真模块进行仿真并给出仿真结果。-In this paper, software-defined radio as the guidance, based on the CORDIC algorithm uses the FPGA platform, digital down-converter design. First analyzes the structure of down-converter and then use a modular design concept, the digital down-conversion function modules including digital controlled oscillator, CIC decimation filtering, HBF decimation filter, FIR low-pass filter for analysis and FPGA design the final In the MATLAB/DSPBuilder under the hardware emulation module simulation and simulation results.
Platform: | Size: 201728 | Author: jiang | Hits:

[VHDL-FPGA-Verilog] verilog

Description: 本代码设计的是一个通讯系统软件无线电中变换比为5/4的分数倍抽取器，用Verilog编程首先实现4倍内插，再实现5倍抽取。-The code design is a software-defined radio communication system in transformation ratio 5/4 points times the extractor, using Verilog programming the first to achieve four times the interpolation, and then taken to achieve five-fold.
Platform: | Size: 4096 | Author: 张霄 | Hits:

[Algorithm] cordic_atan

Description: 用verilog语言实现计算反正切函数，在软件无线电中解调PM/FM中使用的尤为频繁。上传的压缩包是modelsim工程，基于6.5c,里边包含一个完整的PM波产生以及解调过程的matlab文件仿真，并取其中间的I和Q支路做为verilog文件的输入，并将其借条输出与MATLAB实际解调输出作比较。 鉴相器的设计基于CORDIC算法，其精度取决于迭代的深度。由于工程实际运用只需要解调出atan值，并不需要绝对的值，所以并没有给予加权，需要的同学可以自己加上。-Calculated using verilog language arc tangent function, the software radio demodulation PM/FM is particularly used frequently. From the archive is modelsim project, based on 6.5c, inside the PM contains a complete demodulation process of wave generation and simulation matlab file, and whichever is the middle of the I and Q branch verilog file as input, and its IOU demodulated output and actual output of MATLAB for comparison. Phase detector design is based on CORDIC algorithm, its accuracy depends on the iteration depth. As the practical application of engineering demodulated atan value only and does not need absolute value, and there is no weight given to the need of the students can add their own.
Platform: | Size: 79872 | Author: Jorge | Hits:

[VHDL-FPGA-Verilog] quaddecoder_verilog_ise11.2_used_09042010

Description: Two simple Quadrature decoder and Counter build in a XILINX XC9536 CPLD. This Core is coded in Verilog and contains the compete Project file and the fitted quad.jed File. The Pinout is descripted in the Constrained file quad.ucf. To use them, you need teh XC9536 and a clock source that s 4 times faster than the fastes signal that the incremental encoder can creates. IThe clock source frequency is uncritical. For manuel rotated incremental encoder like radio VFO oder other tuning knob, a simple TTL oscillator with about 1Mhz (i use 1.8432Mhz and tested 32768Khz) works brilliant. For very fast decoding, this core is not good enought because there are no Filter FlipFlops are programmed to suppress noises on the Channel A/B Lines.-Two simple Quadrature decoder and Counter build in a XILINX XC9536 CPLD. This Core is coded in Verilog and contains the compete Project file and the fitted quad.jed File. The Pinout is descripted in the Constrained file quad.ucf. To use them, you need teh XC9536 and a clock source that s 4 times faster than the fastes signal that the incremental encoder can creates. IThe clock source frequency is uncritical. For manuel rotated incremental encoder like radio VFO oder other tuning knob, a simple TTL oscillator with about 1Mhz (i use 1.8432Mhz and tested 32768Khz) works brilliant. For very fast decoding, this core is not good enought because there are no Filter FlipFlops are programmed to suppress noises on the Channel A/B Lines.
Platform: | Size: 70656 | Author: JUPP | Hits:

[Other] bpsk

Description: 基于能量检测的频谱感知.由于实际信道中的多径和阴影效应，单个认知用户频谱感知的性能受到影响，因此需要靠不同用户间的协同频谱感知来对抗多径和阴影效应。本设计要求在文中采用一种协作机制，即两用户进行协作频谱感知，提高主用户的检测率，减少检测时间，并且得到捷变增益。要求给出仿真结果。-spectrum sensing in cognitive radio based on energy detection.As the channels in diameter and shadow, not a single user spectrum of capabilities and therefore need different between a user to the spectrum is perceived as more and the effect. this design for the use of a coordination mechanism, the two users collaborate spectrum, the detection rate of increase and decrease the test of time and get a change requires immediate gain. some emulation.
Platform: | Size: 281600 | Author: 林熙怡 | Hits:

[Software Engineering] ddc

Description: 电子科大2009-应用于无线电监测的高速信号处理平台设计，软件无线电的DDC的FPGA实现！-UESTC 2009- applies to wireless monitoring of high-speed signal processing platform design, software radio DDC' s FPGA implementation!
Platform: | Size: 4819968 | Author: peter | Hits:

[VHDL-FPGA-Verilog] usrp_inband_usb_WORKS

Description: 通用软件无线电平台的FPGA代码，非常有用。用Verilog编写-Universal Software Radio Platform FPGA code, very useful. Written by Verilog
Platform: | Size: 974848 | Author: zhoukan | Hits:

[VHDL-FPGA-Verilog] complete

Description: 用Verilog编写的数字钟与汽车尾灯模块。其中数字钟具有时间显示的基本功能，按键校时校分，闹钟模块（包含校时校分），仿电台报时（四低一高），整点报时，12-24显示切换等强大功能。-With a digital clock in Verilog modules and automotive taillights. Digital clock which displays the basic functions of a time, school hours when school keys, alarm clock module (including school hours at school), imitation radio repeater (four low-high), the whole point timekeeping ,12-24 shows switching power.
Platform: | Size: 240640 | Author: Bean | Hits:

[Post-TeleCom sofeware systems] energy_sensing

Description: 认知无线电中频谱检测算法采用能量检测实现，verilog编写的，只有.v文件，需要自己综合编译-Cognitive radio frequency spectrum detection algorithm uses energy detection to achieve, verilog prepared only. V file, needs its own comprehensive compilation
Platform: | Size: 12288 | Author: libo | Hits:

[VHDL-FPGA-Verilog] PC-CFR

Description: 采用matlab simulink编写的消峰参考设计，可以直接生成verilog代码。消峰主要用于降低无线信号的峰均比，提高功放效率。-Clipping prepared using matlab simulink reference design, you can generate verilog code directly. Consumers peak mainly used to reduce radio signal PAR, improve power amplifier efficiency.
Platform: | Size: 2606080 | Author: | Hits:

[Program doc] DCC2010-FPGA-CPU16ASM-DCC

Description: cpu verilog 16 bits to control radio software
Platform: | Size: 81920 | Author: olivier | Hits:

[Documents] homedb

Description: 射频卡协议，射频识别，RFID（Radio Frequency Identification）技术，又称无线射频识别，是一种通信技术，可通过无线电讯号识别特定目标并读写相关数据，而无需识别系统与特定目标之间建立机械或光学接触。(Radio frequency identification, RFID (Radio Frequency Identification) technology, also known as radio frequency identification, is a kind of communication technology, through radio signals to identify specific targets and to read and write data, between without recognition system and the specific goal of establishing a mechanical or optical contact.)
Platform: | Size: 23552 | Author: sssty | Hits:

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