Welcome！[Sign In] ！[Sign Up]！
Front-page it | Collect it | [中国-简体中文]
FAQ Fav
Location:
Search - Verilog noise

Search list

[Other] LDPC

Description: 用于LDPC编码译码的仿真实现。包括随机生成校验矩阵、由校验矩阵产生生成矩阵、编码、加随机噪声、译码等内容。原作者是老外，有部分中文注释。-LDPC coding for decoding Simulation. Check including random matrix generated by the calibration matrix generated generator matrix, coding, plus random noise, such as decoding. The original author is a foreigner, some Chinese Notes.
Platform: | Size: 58368 | Author: 别志松 | Hits:

[MPI] dmf_pn_catch

Description: 采用匹配滤波，实现伪码捕获功能，模块内部可以产生简单噪声来验证捕获性能(verilog)-Matched filter used to achieve pseudo-code capture functionality, the module can generate simple internal noise to verify the performance capture (verilog)
Platform: | Size: 2673664 | Author: 曹旸 | Hits:

[VHDL-FPGA-Verilog] 1111

Description: 基于Verilog-HDL的转子振动噪声电压峰值检测，值得学习啊，-Verilog-HDL based on the rotor vibration noise voltage peak detector, it is worth learning ah,
Platform: | Size: 2299904 | Author: 王朱忠 | Hits:

[matlab] DDC

Description: 用6阶CIC实现，加噪声仿真。序内加详尽注释。-6 bands CIC realized, plus noise simulation. Sequence with a detailed note.
Platform: | Size: 2048 | Author: yeong | Hits:

[Communication-Mobile] fsk

Description: 数字通信中的FSK调制解调的原理和过程, 通过用Matlab 对这一过程的编程,分析信号在理想信道和加噪信道中传输时的时域图, 并用蒙特卡罗算法进行仿真。-Digital communications in FSK modulation and demodulation principle and process, through the use of Matlab in the process of programming, analysis of signals in the ideal channel transmission channel noise and processing time-domain diagram, and Monte Carlo simulation algorithm.
Platform: | Size: 3072 | Author: 李飞 | Hits:

[GPS develop] GPSNaviDataGen_4ch

Description: 基于verilog语言的ＧＰＳ模拟源代码，代码为４颗星，包含噪声信号。-GPS-based Analog Verilog language source code, code for the four stars, including the noise signal.
Platform: | Size: 6144 | Author: Li Gengmin | Hits:

[VHDL-FPGA-Verilog] Verilog_code_for_AWGN

Description: verilog实现awgn信道噪声的代码，支持可变的信噪比。利用移位寄存器来实现伪随机序列。-verilog code for implementation of awgn channel noise. support variable snr. use LSFR to implement the pseudo random sequence.
Platform: | Size: 10555392 | Author: xiejin | Hits:

[VHDL-FPGA-Verilog] medianfilter

Description: 图像滤波中的中值滤波，有效滤除椒盐噪声，使用verilog语言编写-Image filtering in the median filter, effectively filter out salt and pepper noise, using verilog language
Platform: | Size: 3262464 | Author: 钱军 | Hits:

[VHDL-FPGA-Verilog] MATLAB-and-verilog

Description: 1 采用正弦波，方波进行同步调制，实现调制信号、已调信号、解调信号的波形、频谱以及解调器输入输出信噪比的关系。 2 采用Verilog语言编写有符号的五位乘法器 3 实现数字与模拟调制-A sine wave, square wave synchronous modulation to achieve the modulation signal, the modulated signal, the demodulated signal waveform, spectrum and signal to noise ratio of the demodulator input and output relationship. 2 using Verilog language has signed five digital and analog multiplier 3 modulation
Platform: | Size: 559104 | Author: 许学真 | Hits:

[VHDL-FPGA-Verilog] digital-filter

Description: Verilog语言综合的固定频率的数字滤波器，用于滤除夹杂在固定频率信号上的杂波信号，包含了Quaetus工程和仿真文件。-Verilog language integrated fixed-frequency digital filter for filtering out mixed signals at a fixed frequency noise on the signal contains Quaetus engineering and simulation files.
Platform: | Size: 215040 | Author: 张秋光 | Hits:

[Audio program] ANC_LMS

Description: verilog描述的基于LMS的自适应噪声消除器ANC算法。用于数字音频处理。-The verilog Description LMS-based adaptive noise canceller ANC algorithm. For digital audio processing.
Platform: | Size: 3072 | Author: Solomon | Hits:

[Other] m-sequence-of-pseudo-random-noise

Description: 基于verilog 的用于通信系统的m序列伪随机噪声，可综合，我已验证通过。-Based on the verilog for m-sequences of pseudo-random noise of the communication system, can be integrated, I verified through.
Platform: | Size: 14336 | Author: 张阳 | Hits:

[assembly language] ca_prng_latest.tar

Description: Pseudo random noise generator/ implemented in VHDL/Verilog
Platform: | Size: 10240 | Author: ahmed | Hits:

[VHDL-FPGA-Verilog] gwnseq

Description: verilog产生高斯白噪声，gwn_en信号产生使能，gdata是幅度服从高斯分布，功率谱密度为定值的高斯白噪声序列，共10位（现实中只能够做到带限，跟dac输出带宽有关，我的系统只能做到300kHz）-verilog Gaussian white noise, gwn_en signal enabled, gdata amplitude Gaussian distribution, power spectral density of white Gaussian noise sequence value, a total of 10 (in reality can only be band-limited, with dac output bandwidth related, My system can do 300kHz)
Platform: | Size: 1024 | Author: 陈崇毅 | Hits:

[VHDL-FPGA-Verilog] uart_tx

Description: 用Verilog实现通过上位机向串口发送多帧数据，并具有抗噪功能-Implementation serial port receive more frame data by software use Verilog, and has the function of the resist noise
Platform: | Size: 26624 | Author: 熊少 | Hits:

[VHDL-FPGA-Verilog] AWGN_VerilogDesign-master

Description: 加性高斯白噪声生成的VERILOG实现，包含所有的testbench文件。可直接使用-Additive white gaussian noise generated VERILOG realized, including all testbench files. Can be used directly
Platform: | Size: 886784 | Author: 冰城杨松大马首 | Hits:

[VHDL-FPGA-Verilog] noise

Description: 使用FPGA搭建NOISE||内核，在内核基础上进行工程建立。(Using the FPGA to build NOISE || kernel, based on the kernel to build the project.)
Platform: | Size: 19713024 | Author: 湘城旧事 | Hits:

[VHDL-FPGA-Verilog] Verilog语法下载

Description: 介绍verilog语法，详细讲解了Verilog的易错点难点，有较好的知道效果(It is used to measure noise and detect road noise pollution. It is accurate and has good effect.)
Platform: | Size: 301056 | Author: 庄杰 | Hits:

[VHDL-FPGA-Verilog] elecfans.com-verilog教程书

Description: 从入门到精通，从简单到难，带你轻轻松松玩转FPGA(It is used to measure noise and detect road noise pollution. It is accurate and has good effect.)
Platform: | Size: 4169728 | Author: 庄杰 | Hits:

CodeBus www.codebus.net