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[VHDL-FPGA-Verilog] modu

Description: this the verilog code that performs the modulus function ... most importantly it is synthesisable... uses the repeated sub algorithm-this is the verilog code that performs the modulus function ... most importantly it is synthesisable... uses the repeated sub algorithm
Platform: | Size: 415744 | Author: mma32 | Hits:

[Embeded-SCM Develop] LIP2301CORE_Synthesisable-RAM

Description: Verilog Synthesisable RAM source code
Platform: | Size: 214016 | Author: jc | Hits:

[VHDL-FPGA-Verilog] rom_verilog

Description: verilog 源代码，非常简单的一种ROM的可综合的写法，适合新手学习之用。-verilog source code，simply implementation of ROM with synthesisable coding-sytle， special for the beginners.
Platform: | Size: 1024 | Author: 李海华 | Hits:

[VHDL-FPGA-Verilog] sram_verilog

Description: verilog 源代码，非常简单的一种SRAM的可综合的写法，适合新手学习之用。-verilog source code，simply implementation of SRAM with synthesisable coding-sytle， special for the beginners.
Platform: | Size: 1024 | Author: 李海华 | Hits:

[VHDL-FPGA-Verilog] Verilog_primer_V1.1

Description: Verilog HDL 语言的编码规范。详细介绍了verilog HDL编码的注意事项和基本规范。分为可综合部分，仿真专用部分以及nc-verilog仿真环境的建立。-Description of Verilog HDL coding. containing synthesisable language, simulationable language and how to construct a proper environment.
Platform: | Size: 745472 | Author: Venture Zhao | Hits:

[Other] lpddr_verilog_model

Description: 美光 ddr sdram 仿真模型， 不可综合，用在测试平台模仿ddr sdram的功能。verilog语言编写。-Micron MOBILE DDR SDRAM simulation model. not synthesisable, used in tesetbench to emulation the function of ddr sdram. written in verilog
Platform: | Size: 39936 | Author: qiubin | Hits:

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