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[VHDL-FPGA-Verilog] Design_and_Test_VerilogHDL

Description: Design and Test_Verilog HDL——EDA先锋工作室《设计与验证—Verilog HDL》配书源代码，很多使用的实例，并有说明，是学习Verilog 不可多得的好资料。-Design and Test_Verilog HDL- EDA pioneer studio design and verification-Verilog HDL book with source code, many examples and has made it clear that it is rare to learn Verilog good information.
Platform: | Size: 1887232 | Author: ZY | Hits:

[VHDL-FPGA-Verilog] mini-uart

Description: Verilog实现mini-uart，代码经过FPEG验证，含文档及流程图。-Verilog implementation mini-uart, code FPEG After verification, including documentation and flow chart.
Platform: | Size: 253952 | Author: serein | Hits:

[SCM] DW8051(Verilog)

Description: 51单片机IP核源码，可以在fpga实现，并进行仿真与验证-51 single-chip IP nuclear source, you can achieve the fpga, and simulation and verification
Platform: | Size: 67584 | Author: xuhuifeng | Hits:

[Other] Design_and_verification_verilog_hdl

Description: 设计与验证verilog hdl配套光盘-Design and verification verilog hdl" supporting CD-ROM
Platform: | Size: 2042880 | Author: zhc | Hits:

[VHDL-FPGA-Verilog] sim

Description: 通用的循环码编码器和（7,4）循环码译码器。采用VERILOG HDL编写，通过硬件验证。需使用modelsim 5.6仿真-Common cyclic code encoder and (7,4) cyclic code decoder. VERILOG HDL preparation used by the hardware verification. Need to use simulation modelsim 5.6
Platform: | Size: 33792 | Author: 来来 | Hits:

[Other] ovm-2.0.2

Description: OVM(Open Verification Methdology) for system verilog or systemC
Platform: | Size: 3027968 | Author: ASURA | Hits:

[Other] algorithm_design_and_logic_implemention

Description: 本书作者为夏宇文，详细讲解了从算法设计与验证到硬件逻辑实现的过程，要求读者有一定的verilog基础-This book author XIA Yu-Wen gave a detailed account from algorithms to hardware logic design and verification of implementation process, requiring readers to have some basis for verilog
Platform: | Size: 832512 | Author: neo | Hits:

[VHDL-FPGA-Verilog] Chapter11-13

Description: 第十一章到第十三章的代码 本书通过100多个模块实例，详细地讲解了Verilog HDL程序设计语言，全书共分13章，内容涉及VerilogHDL语言基本概念、建模、同步设计、异步设计、功能验证等，实例包括各种加法器/计数器、乘法器/除法器、编码器/译码器、状态机、SPIMaster Controller、I2C Master controller、CAN ProtocolController、Memory模块、JPEG图像压缩模块、加密模块、ATA控制器、8位RISC-CPU等及各个实例模块相应的Testbench，所举实例具有很强的实用性和代表性，每个实例均给出了介绍、功能分析、程序代码和结果演示。-Chapter XI to the 13th chapter of the code in this book through more than 100 module instance, explain in detail the Verilog HDL programming language, the book is divided into 13 chapters, covering basic concepts VerilogHDL languages, modeling, synchronous design, asynchronous design, functional verification, etc. Examples include a variety of adder/counter, multiplier/divider, encoders/decoders, state machines, SPIMaster Controller, I2C Master controller, CAN ProtocolController, Memory modules, JPEG image compression module, encryption module, ATA controller, 8-bit RISC-CPU, etc. and the various instances of the corresponding module Testbench, The examples are highly practical and representation, each instance of it all gives the introduction, functional analysis, program code and results presentation.
Platform: | Size: 5088256 | Author: xiao | Hits:

[VHDL-FPGA-Verilog] SystemVerilogEventRegionsRaceAvoidanceGuidelines.r

Description: The IEEE1800 SystemVerilog Standard includes new event regions primarily added to reduce race conditions between verification code and SystemVerilog designs. The new regions also facilitate race-free Assertion Based Verification (ABV). This paper details common Verilog verification strategies and how the new event regions facilitate construction of race-free testbenches using new SystemVerilog capabilities. An in- depth explanation of SystemVerilog event regions is included to help understand how race- reduction goals have been met. Important design & testbench coding guidelines are also included.-The IEEE1800 SystemVerilog Standard includes new event regions primarily added to reduce race conditions between verification code and SystemVerilog designs. The new regions also facilitate race-free Assertion Based Verification (ABV). This paper details common Verilog verification strategies and how the new event regions facilitate construction of race-free testbenches using new SystemVerilog capabilities. An in- depth explanation of SystemVerilog event regions is included to help understand how race- reduction goals have been met. Important design & testbench coding guidelines are also included.
Platform: | Size: 356352 | Author: 陈斌 | Hits:

[Other] Verilog

Description: 该代码是Veriloghdl语言实现的串口通信，经过FPGA板子下载验证通过，读者可以使用-The code is Veriloghdl language of the serial communications, after verification by FPGA board download, readers can use
Platform: | Size: 194560 | Author: 雪晨 | Hits:

[VHDL-FPGA-Verilog] Sdram_Control_2Port

Description: 双端口SDRAM控制器，将SDRAM虚拟成两个端口，已经在ALTER DE2开发板的硬件上验证通过，采用Verilog HDL语言编写。-Dual-port SDRAM controller, SDRAM virtual into two ports, have ALTER DE2 development board hardware verification by using the Verilog HDL language.
Platform: | Size: 11264 | Author: | Hits:

[VHDL-FPGA-Verilog] verilog

Description: 一个很好的关于verilog的PPT 第1章 EDA设计与Verilog HDL语言概述 第2章 Verilog HDL基础与开发平台操作指南 第3章 Verilog HDL程序结构 第4章 VERILOG HDL语言基本要素 第5章 面向综合的行为描述语句 第6章 面向验证和仿真的行为描述语句 第7章 系统任务和编译预处理语句 第8章 VERILOG HDL可综合设计的难点解析 第9章 高级逻辑设计思想与代码风格 第10章 可综合状态机开发实例 第11章 常用逻辑的VERILOG HDL实现 第12章 XILINX硬核模块的VERILOG HDL调用 第13章 串口接口的VERILOG HDL设计-A good verilog of PPT on Chapter 1 of EDA Design and Verilog HDL language outlined in Chapter 2 based on Verilog HDL and development platform Operations Guide Chapter 3 Verilog HDL program structure VERILOG HDL languages Chapter 4 Chapter 5 for the basic elements of an integrated behavioral description statement in Chapter 6 for the verification and simulation of the behavior of the system described in Chapter 7 mission statements and prepared statements compiled in Chapter 8 VERILOG HDL design can be integrated Difficulties in Chapter 9, advanced logic design and coding style Chapter 10 Comprehensive state machine instance can be developed in Chapter 11 to achieve common logic VERILOG HDL Chapter 12 XILINX hard core module VERILOG HDL called Chapter 13 Serial Interface VERILOG HDL design
Platform: | Size: 27825152 | Author: lyy | Hits:

[VHDL-FPGA-Verilog] Testbench(Verilog)

Description: verilog验证平台的使用 很不错 很详细 想具体-verilog verification platform is more like using a very good specific
Platform: | Size: 350208 | Author: guoguo | Hits:

[VHDL-FPGA-Verilog] SystemVerilog-for-Verification--2nd-Ed

Description: This a system verilog book.-This is a system verilog book.
Platform: | Size: 1946624 | Author: sikki | Hits:

[VHDL-FPGA-Verilog] sv-for-Verification-2nd

Description: System Verilog for Verification, 2nd Edition.非常经典的资料，供IC开发的人员作自测平台或者验证的人员使用-System Verilog for Verification, 2nd Edition. Very classic information for IC self-test platform for the development of personnel for use by or verification
Platform: | Size: 1982464 | Author: linhaidu | Hits:

[VHDL-FPGA-Verilog] Verilog-Digital-System-Design

Description: Verilog数字系统设计——RTL综合.测试平台与验证 书中的所有源代码-Verilog Digital System Design- RTL synthesis. Test and verification platform for all the source code for the book
Platform: | Size: 8890368 | Author: 鲁智深 | Hits:

[File Format] verilog-ieee.pdf.tar

Description: IEEE 2001 verilog 标准 ,详细讲述了 业内 公认的 VERILOG 标准 ,-The Verilog¤ Hardware Description Language (Verilog HDL) became an IEEE standard in 1995 as IEEE Std 1364-1995. It was designed to be simple, intuitive, and effective at multiple levels of abstraction in a standard textual format for a variety of design tools, including verification simulation, timing analysis, test analysis, and synthesis. It is because of these rich features that Verilog has been accepted to be the language of choice by an overwhelming number of IC designers.
Platform: | Size: 2200576 | Author: adam | Hits:

[VHDL-FPGA-Verilog] system-verilog-books

Description: SYSTEM VERILOG FOR VERIFICATION BOOK
Platform: | Size: 16860160 | Author: subeg | Hits:

[VHDL-FPGA-Verilog] verilog--divide-programs

Description: verilog任意分频程序，包括奇数倍分频和偶数倍分频，占空比为50 ，QuartusII上验证程序有效-verilog every divide programs, including an odd multiple divider and even multiple frequency, duty cycle 50 , the QuartusII on the verification process
Platform: | Size: 578560 | Author: ni husheng | Hits:

[VHDL-FPGA-Verilog] Alter官方FFT程序(使用Verilog编写)

Description: 其主要使用verilog编写fft程序主体，之后通过quartus和matlab实现对fft程序的测试，可以很好做到自动化验证(The main use of verilog prepared fft main program, and then achieved by quartus and matlab fft program testing, you can do a good job of automated verification)
Platform: | Size: 995328 | Author: 未曾走远 | Hits:
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