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[Other resource] wishbone_i2c_master

Description: -- WISHBONE revB2 compiant I2C master core -- -- author: Richard Herveille -- rev. 0.1 based on simple_i2c -- rev. 0.2 april 27th 2001, fixed incomplete sensitivity list on assign_dato process (thanks to Matt Oseman) -- rev. 0.3 may 4th 2001, fixed typo rev.0.2 txt -> txr -- rev. 0.4 may 8th, added some remarks, fixed some sensitivity list issues--- WISHBONE revB2 compiant I2C master core -- -- author : Richard Herveille -- rev. 0.1 based on simple_i 2c -- rev. 0.2 adolescence 27th 2001, fixed incomplete sensitivity list on assign_d ato process (thanks to Matt Oseman) -- rev. 0.3 m ay 4th 2001, fixed typo rev.0.2 txt -
Platform: | Size: 5470 | Author: 郑开科 | Hits:

[Com Port] wishbone_i2c_master_vhd

Description: WISHBONE revB2 compiant I2C master core
Platform: | Size: 5807 | Author: weixing | Hits:

[Other resource] wb_rtc

Description: // -*- Mode: Verilog -*- // Filename : wb_master.v // Description : Wishbone Master Behavorial // Author : Winefred Washington // Created On : 2002 12 24 // Last Modified By: . // Last Modified On: . // Update Count : 0 // Status : Unknown, Use with caution! // Description Specification // General Description: 8, 16, 32-bit WISHBONE Master // Supported cycles: MASTER, READ/WRITE // MASTER, BLOCK READ/WRITE // MASTER, RMW // Data port, size: 8, 16, 32-bit // Data port, granularity 8-bit // Data port, Max. operand size 32-bit // Data transfer ordering: little endian // Data transfer sequencing: undefined
Platform: | Size: 8076 | Author: 姓名 | Hits:

[VHDL-FPGA-Verilog] wishbone_i2c_master

Description: -- WISHBONE revB2 compiant I2C master core -- -- author: Richard Herveille -- rev. 0.1 based on simple_i2c -- rev. 0.2 april 27th 2001, fixed incomplete sensitivity list on assign_dato process (thanks to Matt Oseman) -- rev. 0.3 may 4th 2001, fixed typo rev.0.2 txt -> txr -- rev. 0.4 may 8th, added some remarks, fixed some sensitivity list issues--- WISHBONE revB2 compiant I2C master core---- author : Richard Herveille-- rev. 0.1 based on simple_i 2c-- rev. 0.2 adolescence 27th 2001, fixed incomplete sensitivity list on assign_d ato process (thanks to Matt Oseman)-- rev. 0.3 m ay 4th 2001, fixed typo rev.0.2 txt-
Platform: | Size: 5120 | Author: 郑开科 | Hits:

[Com Port] wishbone_i2c_master_vhd

Description: WISHBONE revB2 compiant I2C master core
Platform: | Size: 5120 | Author: weixing | Hits:

[MiddleWare] opencores_i2c_master

Description: i2c VHDL,能够实现I2C 用的是wishbone总线
Platform: | Size: 193536 | Author: wang | Hits:

[VHDL-FPGA-Verilog] wb_rtc

Description: // -*- Mode: Verilog -*- // Filename : wb_master.v // Description : Wishbone Master Behavorial // Author : Winefred Washington // Created On : 2002 12 24 // Last Modified By: . // Last Modified On: . // Update Count : 0 // Status : Unknown, Use with caution! // Description Specification // General Description: 8, 16, 32-bit WISHBONE Master // Supported cycles: MASTER, READ/WRITE // MASTER, BLOCK READ/WRITE // MASTER, RMW // Data port, size: 8, 16, 32-bit // Data port, granularity 8-bit // Data port, Max. operand size 32-bit // Data transfer ordering: little endian // Data transfer sequencing: undefined-//-*- Mode: Verilog-*- // Filename : wb_master.v // Description : Wishbone Master Behavorial // Author : Winefred Washington // Created On : 2002 12 24 // Last Modified By: . // Last Modified On: . // Update Count : 0 // Status : Unknown, Use with caution! // Description Specification // General Description: 8, 16, 32-bit WISHBONE Master // Supported cycles: MASTER, READ/WRITE // MASTER, BLOCK READ/WRITE // MASTER, RMW // Data port, size: 8, 16, 32-bit // Data port, granularity 8-bit // Data port, Max. operand size 32-bit // Data transfer ordering: little endian // Data transfer sequencing: undefined
Platform: | Size: 8192 | Author: 姓名 | Hits:

[VHDL-FPGA-Verilog] wishbone_i2c_master_vhd

Description: wishbone i2c master vhdl code
Platform: | Size: 5120 | Author: 磊 | Hits:

[Communication-Mobile] wb_lpc_latest.tar

Description: Wishbone to LPC (Low-Pin Count) Bridge, includes master and slave modules. Supports 8-bit I/O Read and Write cycles, 8-bit Memory Read/Write cycles, DMA cycles, and up to 32-bit Firmware memory read/write cycles. Serial IRQ support is also provided. None of this has been tested (yet) with a third-party LPC Peripheral or Host.
Platform: | Size: 410624 | Author: Arun | Hits:

[VHDL-FPGA-Verilog] pif2wb_latest.tar

Description: This is a bridge IP core to interface the Tensilica PIF bus protocol with the OpenCores WishBone. It currently supports single-cycle as well as burst transfer operations. The core has been tested in a master-PIF slave-WB configuration.-This is is a bridge IP core to interface the Tensilica PIF bus protocol with the OpenCores WishBone. It currently supports single-cycle as well as burst transfer operations. The core has been tested in a master-PIF slave-WB configuration.
Platform: | Size: 2256896 | Author: Arun | Hits:

[Other] spi_master

Description: SPI wishbone master and verification environment
Platform: | Size: 2506752 | Author: 王小墨 | Hits:

[VHDL-FPGA-Verilog] wishbone_m4_s8

Description: wishbone 骨幹部份 RTL 源碼, 以verilog 寫成, 自創. 支源 4 master 及 8 slave-wishbone core, write by verilog, support 4 master and 8 slaver. language: verilog.
Platform: | Size: 3072 | Author: mis_hey | Hits:

[VHDL-FPGA-Verilog] spi_latest[1].tar

Description: serial peripheral interface master interface Wishbone compatible
Platform: | Size: 2623488 | Author: hr | Hits:

[SCM] i2c_latest[1].tar

Description: I2C is a two-wire, bidirectional serial bus that provides a simple, efficient method of data exchange between devices. It is primarily used in the consumer and telecom market sector and as a board level communications protocol. The OpenCores I2C Master Core provides an interface between a Wishbone Master and an I2C bus.
Platform: | Size: 1479680 | Author: zhong | Hits:

[Software Engineering] wishbone-slave-and-master-to-avalon-bus

Description: wishbone slave and master to avalon bus verilog
Platform: | Size: 1024 | Author: lamqsb | Hits:

[VHDL-FPGA-Verilog] i2c_latest.tar

Description: i2C总线的控制器核，实现了I2C的主站功能。-I2C is a two-wire, bidirectional serial bus that provides a simple, efficient method of data exchange between devices. It is primarily used in the consumer and telecom market sector and as a board level communications protocol. The OpenCores I2C Master Core provides an interface between a Wishbone Master and an I2C bus. It is an easy path to add I2C capabilities to any Wishbone compatible system. You can find the I2C specifications on Phillips web Site. Work was originally started by Frédéric Renet.
Platform: | Size: 1479680 | Author: | Hits:

[VHDL-FPGA-Verilog] wishbone

Description: Wishbone规范具有如下特点:简单、紧凑，需要很少的逻辑门 完整的普通数据据传输总线协议，包括单个读写、快传输、读一修改一写周期、事件周期 数据总线宽度可以是8-64位 支持大端(big-endian)和小端(litle-endian)，接口自动完成两者之间的转换。支持存储器映射、FIFO存储器、交叉互联 握手协议，允许速率控制 可以达到每个时钟周期进行一次数据传输 支持普通周期结束、重试结束、错误结束等总线周期形式 支持用户自定义的标志:采用MASTER/SLAVE体系结构 支持多点进程(Multi-MASTER):仲裁算法用于定义 支持各种各样的IP核互联，包括USB、双向总线、复用器互联等 同步逻辑设计 非常简单的时序标准 与硬件实现技术无关(FPGA, ASIC等) 与设计工具无关。 相对于其他的IP核接口规范来说，Wishbone接口规范具有简单、开放、高效、利于实现等特点而且完全免费，并没有专利保护。基于上述优点，因此采用Wishbone总线进行接口设计。本文对Wishbone总线接口的设计参考了OpenCore上的有关设计。- Wishbone specification has the following characteristics : a simple , compact, and requires very little logic gates complete common data bus data transfer protocols, including single reader , fast transmission, read-modify- write cycle, the event cycle data bus width can be 8-64 bit support big-endian (big-endian) and the small end (litle-endian), the interface automatically convert between the two. Support memory mapping , FIFO memory , cross interconnection handshake protocol that allows rate control every clock cycle to achieve a data transfer support normal cycle ends , retry the end , wrong end of the bus cycle and other forms support for user-defined flags : The MASTER/SLAVE architecture supports multi- process (Multi-MASTER): arbitration algorithm is used to define support a variety of IP cores interconnected , including USB, bi-directional bus , multiplexer interconnection , etc. synchronous logic design very simple timing standards technology-indepe
Platform: | Size: 12288 | Author: 程浩武 | Hits:

[Other] wb_master

Description: this the wishbone master interface to connect with wishbone slave and a clock module-this is the wishbone master interface to connect with wishbone slave and a clock module
Platform: | Size: 1024 | Author: Duy | Hits:

[VHDL-FPGA-Verilog] gpio-master

Description: 基于WISHBONE总线接口的GPIO模块verilog代码实现，包含详细GPIO定义文档，testbench，RTL仿真与综合环境-WISHBONE interface to GPIO verilog code, GPIO define, RTL sim, syn
Platform: | Size: 419840 | Author: lv | Hits:

[VHDL-FPGA-Verilog] i2c_wishbone.tar

Description: verilog i2c master wishbone slave wrapper
Platform: | Size: 4096 | Author: ascensor | Hits:
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