Search - XILINX I

Search - XILINX I - List

[SCM] oc8051 DL : 0: 51的VERILOG代码！适用于Xilinx的FPGA-51 VERILOG code! In Xilinx FPGA
Update : 2025-02-17 Size : 1.16mb Publisher : 林建加
[VHDL-FPGA-Verilog] I2C总线控制器 Xilinx提供 DL : 0: 用Verilog HDL实现I2C总线功能，对I2C总线有很大帮助-I2C bus contrll functions implemented by Verilog HDL.
Update : 2025-02-17 Size : 869kb Publisher : 司法
[Other] XilinxJTAF DL : 0: XilinxJTAG.rar xilinx CPLD,FPGA的JTAG口使用说明.-XilinxJTAG.rar Xilinx CPLD, FPGA JTAG I use.
Update : 2025-02-17 Size : 421kb Publisher :
[VHDL-FPGA-Verilog] fixed_pointDivider DL : 0: 本人编写的定点除法器,开发软件为XILINX的ISE6.2,通过PAR仿真.-I prepared for the sentinel division, the development of software for the ISE6.2 Xilinx, PAR through simulation.
Update : 2025-02-17 Size : 388kb Publisher : litao
[VHDL-FPGA-Verilog] simple_fm_receiver.tar DL : 0: FM收音机的解码及控制器VHDL语言实现，Xilinx提供的．别谢我．-FM radio decoder and controller VHDL, Xilinx provide. I thank other.
Update : 2025-02-17 Size : 69kb Publisher : 喻袁洲
[Software Engineering] I2CAnalyzeReport DL : 0: XILINX IIC总线设计分析我的实验报告-XILINX IIC bus design and analysis of the report I
Update : 2025-02-17 Size : 323kb Publisher : 真诚的猪
[Software Engineering] Virtex.files DL : 0: 在FPGA系统设计中，要达到性能最大化需要平衡具有混合性能效率的元器件，包括逻辑构造(fabric)、片上存储器、DSP和I/O带宽。在本文中，我将向你解释怎样能在追求更高系统级性能的过程中受益于Xilinx® 的Virtex™ -5 FPGA构建模块，特别是新的ExpressFabric™ 技术。以针对逻辑和算术功能的量化预期性能改进为例，我将探究ExpressFabric架构的主要功能。基于实际客户设计的基准将说明Virtex-5ExpressFabric技术性能平均比前一代Virtex-4 FPGA要高30％。-in FPGA system design to achieve maximum performance with the need to balance the efficiency of the mixed performance components including logical structure (fabric), on-chip memory, DSP and I/O bandwidth. In this article, I will explain how you can in the pursuit of higher system-level performance of the process to benefit from Xilinx
Update : 2025-02-17 Size : 95kb Publisher : yaoming
[Software Engineering] Xilinx_ISE_chinese DL : 0: Xilinx ISE的中文教程,十分易懂,包你学会,当初我就是靠这个学的-Xilinx ISE Chinese guides, very easy to understand, including the Institute of you, when I was on the school
Update : 2025-02-17 Size : 913kb Publisher : 何思涵
[VHDL-FPGA-Verilog] myUART DL : 0: 这是我用Xilinx公司的sparten3开发板,ISE集成开发环境，用VHDL语言开发的串口全双工通信程序，供大家参考，共同学习。-This is the company I used the sparten3 Xilinx development boards, ISE Integrated Development Environment, Using VHDL development of the full-duplex serial communication program, for your reference, learning together.
Update : 2025-02-17 Size : 642kb Publisher : 汪莉莉
[VHDL-FPGA-Verilog] I2C_loader DL : 0: 用FPGA做主控制器，对IIC从设备配置参数的源程序。Xilinx提供-FPGA master controller, right from the IIC equipment configuration parameters of the source. Xilinx offer
Update : 2025-02-17 Size : 91kb Publisher : cloud
[Embeded-SCM Develop] 8051forxilinx DL : 0: 我在spartan-3e starter kit 的板上实现了mc8051，程序调试通过，运行正常。方法 1、用Keil 编译8051的代码； 2、将生成的hex文件用hex->bin工具转成bin文件 3、用bin－>coe工具转成coe 4、在core generate 生成的rom中指明coe文件的位置 5、编译、下载到spartan-3e starter kit 板上，你将会看到流水灯的效果我正在做这方面的东西，欢迎大家与我一起探讨。-I spartan- 3e of the starter kit board realized mc8051. through debugging procedures, operating normally. A method of using the Keil compiler code 8051; 2, will produce the documents hex hex-
Update : 2025-02-17 Size : 594kb Publisher : lanty
[Embeded-SCM Develop] 3128 DL : 0: cpld3128开发板的原理图很有用,已经做成PCB,需要的话可以联系我-cpld3128 development board diagram useful to have caused PCB, the need to be contacted I
Update : 2025-02-17 Size : 149kb Publisher : qxl
[DSP program] DTK-IO DL : 0: 数字I/O实验主要完成的功能：在此实验中，SEED-DEC5416 首选进行初始化，包括对外设 UART、本身频率的设定及一些状态区的初始化。然后等待 SEED-MMI5402 发送命令；SEED－DEC5416 响应交通灯自动模式、交通灯手动手动模式、交通灯东西通、交通灯南北通、及交通灯的禁行与夜间模式的操作命令。同时还响应，对 SEED-DEC5416 的复位及两个单元之间的通讯故障。 -Digital I/O completion of the experiment the main features: In this experiment, SEED-DEC5416 preferred to initialize, including peripherals UART, their frequency settings and some of the initialization state of the district. SEED-MMI5402 and then wait to send commands SEED-DEC5416 automatic mode in response to traffic lights, traffic lights manual manual mode, the traffic light east-west pass, pass traffic lights north and south, and traffic lights at night and cut-line mode command. At the same time, also responded to the SEED-DEC5416 reset and communication between two modules fault.
Update : 2025-02-17 Size : 217kb Publisher : sylivian
[SCM] XilinxGuide DL : 0: 对有学习XINLIN芯片的同志有很好的帮助，这是份资料，供大家下载看看，这也是我经常用到的-On-chip learning XINLIN comrades have a very good help, this is information for everyone to download and see, that is what I frequently used
Update : 2025-02-17 Size : 6.7mb Publisher : wangjinming
[VHDL-FPGA-Verilog] clock DL : 0: 自己编写的一个verilog时钟程序，在xilinx的ISE仿真通过-I have written a Verilog clock procedures, in Xilinx s ISE simulation through
Update : 2025-02-17 Size : 320kb Publisher : lg
[VHDL-FPGA-Verilog] task_function DL : 0: 自己编写的一个verilog HDL小程序，实现基本的task调用function的功能，对初学者有用。在xilinx的ISE仿真调试通过-I have written a verilog HDL small procedures, to achieve the basic function of the task to call the function, useful for beginners. In Xilinx s ISE simulation debugging through
Update : 2025-02-17 Size : 230kb Publisher : lg
[VHDL-FPGA-Verilog] xilinx_iic_spi DL : 0: xlinx官方的iic和spi接口的描述-IIC and xlinx official description of spi interface
Update : 2025-02-17 Size : 1.68mb Publisher : 杨子树
[VHDL-FPGA-Verilog] FPGAbi_ioreseach DL : 0: :针对现场可编程门阵列(FPGA)芯片的特点,研究FPGA中双向端口I/O的设计,同时给出仿真初始化双向端口I/O的方法。采用这种双向端口的设计方法,选用Xilinx的Spartan2E芯片设计一个多通道图像信号处理系统。-: For field programmable gate array (FPGA) chip features of FPGA in the bi-directional port I/O design, the simulation is initialized at the same time two-way port I/O method. Using this design method of two-way ports, optional Spartan2E the Xilinx chip to design a multi-channel image signal processing system.
Update : 2025-02-17 Size : 113kb Publisher : zhanyi
[VHDL-FPGA-Verilog] I2CController DL : 0: Xilinx的I2C总线控制器，verilog版本，文档号是XAPP333，可到Xilinx网上查找具体说明，有对应的VHDL版本的-Xilinx
Update : 2025-02-17 Size : 22kb Publisher : iversn
[VHDL-FPGA-Verilog] ise9.1 DL : 0: 学习ISE的好资料，想要使用XILINX芯片进行开发必看-ISE learning good information, want to use a must-see XILINX chip development
Update : 2025-02-17 Size : 25.74mb Publisher : 李鹏

« 12 3 4 5 »