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[Other resource] uart766

Description: ---实现的部分VHDL 程序如下。 　　--- elsif clk1x event and clk1x = 1 then ---if std_logic_vector(length_no) >= “0001” and std_logic_vector(length_no) <= “1001” then -----数据帧数据由接收串行数据端移位入接收移位寄存器---rsr(0) <= rxda --- rsr(7 downto 1) <= rsr(6 downto 0) --- parity <= parity xor rsr(7) --- elsif std_logic_vector(length_no) = “1010” then --- rbr <= rsr --接收移位寄存器数据进入接收缓冲器--- ...... --- end if---- achieve some VHDL procedure is as follows. --- Elsif clk1x event and then a clk1x = s --- if td_logic_vector (length_no)
Platform: | Size: 157261 | Author: 766 | Hits:

[Software Engineering] uart766

Description: ---实现的部分VHDL 程序如下。 　　--- elsif clk1x event and clk1x = 1 then ---if std_logic_vector(length_no) >= “0001” and std_logic_vector(length_no) <= “1001” then -----数据帧数据由接收串行数据端移位入接收移位寄存器---rsr(0) <= rxda --- rsr(7 downto 1) <= rsr(6 downto 0) --- parity <= parity xor rsr(7) --- elsif std_logic_vector(length_no) = “1010” then --- rbr <= rsr --接收移位寄存器数据进入接收缓冲器--- ...... --- end if---- achieve some VHDL procedure is as follows.--- Elsif clk1x event and then a clk1x = s--- if td_logic_vector (length_no)
Platform: | Size: 156672 | Author: | Hits:

[VHDL-FPGA-Verilog] DE2_VGA3

Description: The VGA example generates a 320x240 diffusion-limited-aggregation (DLA) on Altera DE2 board. A DLA is a clump formed by sticky particles adhering to an existing structure. In this design, we start with one pixel at the center of the screen and allow a random walker to bounce around the screen until it hits the pixel at the center. It then sticks and a new walker is started randomly at one of the 4 corners of the screen. The random number generators for x and y steps are XOR feedback shift registers (see also Hamblen, Appendix A). The VGA driver, PLL, and reset controller from the DE2 CDROM are necessary to compile this example. Note that you must push KEY0 to start the state machine. -The VGA example generates a 320x240 diffusion-limited-aggregation (DLA) on Altera DE2 board. A DLA is a clump formed by sticky particles adhering to an existing structure. In this design, we start with one pixel at the center of the screen and allow a random walker to bounce around the screen until it hits the pixel at the center. It then sticks and a new walker is started randomly at one of the 4 corners of the screen. The random number generators for x and y steps are XOR feedback shift registers (see also Hamblen, Appendix A). The VGA driver, PLL, and reset controller from the DE2 CDROM are necessary to compile this example. Note that you must push KEY0 to start the state machine.
Platform: | Size: 1275904 | Author: Donghua Gu | Hits:

[VHDL-FPGA-Verilog] alu

Description: 用VHDL实现8种运算的ALU，带鱼不带符号的加减乘除，与或异或和求反-Use VHDL to achieve the eight kinds of computing ALU, hairtail unsigned addition and subtraction, multiplication and division, with or XOR and seek anti-
Platform: | Size: 1024 | Author: helen | Hits:

[Crack Hack] CRC

Description: 通过对于模2除法的研究 可以得到如下方法： 1． 把信息码后面加上p－1位的0，这个试验中p是6位，即在输入的信息码后面加上“00000”。把这个17位的被除数放入input中。 2． 在得到被除数input之后，设计一个在被除数上移动的数据滑块变量d，把input中的最高位开始逐次复制给变量d。 3． 如果d的最高位为1，由变量d和变量p做异或运算；如果d的最高位为0则不运算或者做多余的异或‘0’的运算。 4． 把滑块变量d往后滑动一位。 5． 循环步骤（3，4）11次。 6． 执行步骤3。 7． 得到余数c，把c转成信号输出。 -Through the 2-mode research division will be as follows: 1. Information code followed by the p-1-bit 0, this test p is 6, that is, the information in the input code after 00000. This 17 Add input in the dividend. 2. After receiving input dividend, dividend on the design of a mobile data slider variable d, the highest input in the beginning of successive copied to the variable d. 3. If the highest d for 1, by the variable d and variable p do XOR operations if d the highest computing to 0 or do not redundant XOR 0 arithmetic. 4. The slider sliding variable d next one. 5. Cycle of steps (3,4) 11. 6. Steps 3.7. Be more than a few c, the c into the output signal.
Platform: | Size: 6144 | Author: lijq | Hits:

[VHDL-FPGA-Verilog] ALU

Description: 在Xilinx7.1平台下编写的ALU代码，可以实现五位加法、减法、与、异或四种运算！-Xilinx7.1 platform in the preparation of the ALU code, can be achieved five adder, subtraction, and, four computing XOR!
Platform: | Size: 1024 | Author: 梁晓炬 | Hits:

[Other] vhdlcodes

Description: with this rar file i am sending five source codes in vhdl for xor gate,xor gate using tristae gate,electronic voting machine,mod 16 counter,jk flip flop.please accept these codes and make me member of this site.so that i can download code from this site also.i really needed codes please accept that as soon as possible.
Platform: | Size: 2048 | Author: nitin | Hits:

[VHDL-FPGA-Verilog] xor

Description: 异或门的FPGA实现的verilog代码-xor FPGA realization of the verilog code
Platform: | Size: 3072 | Author: 胡兵 | Hits:

[VHDL-FPGA-Verilog] my_xor

Description: 异或门，Verilog实现，包含实验说明文档。-XOR gate, Verilog implementation, including test documentation.
Platform: | Size: 893952 | Author: 姚成富 | Hits:

[VHDL-FPGA-Verilog] communications_1

Description: 用vhdl代码描述的通信系统仿真程序。包括信源（20位m序列），crc编码（采用串行算法），加噪（用22位m序列产生稀疏的1，然后和编码后的数据异或）。-Vhdl code with the simulation program described in the communication system. Including the source (20 m sequence), crc code (using the serial algorithm), noise (with 22 m sequence generated sparse 1, then the encoded data and XOR).
Platform: | Size: 483328 | Author: 李修函 | Hits:

[VHDL-FPGA-Verilog] communications_2

Description: 用vhdl代码描述的通信系统仿真程序。包括信源（20位m序列），crc编码（采用串行算法），加噪（用22位m序列产生稀疏的1，然后和编码后的数据异或），crc解码，数据串行输出。 -Vhdl code with the simulation program described in the communication system. Including the source (20 m sequence), crc code (using the serial algorithm), noise (with 22 m sequence generated sparse 1, then the encoded data and XOR), crc decoding, serial output data.
Platform: | Size: 120832 | Author: 李修函 | Hits:

[VHDL-FPGA-Verilog] XOR

Description: vhdl code for XOR gate
Platform: | Size: 9216 | Author: vasu | Hits:

[VHDL-FPGA-Verilog] sdsdsd

Description: Cpu 8bit. Vorks good. Taking all instructions, sdo OR Xor and athor... Is registers
Platform: | Size: 8192 | Author: kaktusasturbo | Hits:

[VHDL-FPGA-Verilog] xor

Description: Xor gate implementation in vhdl.
Platform: | Size: 6144 | Author: aryan | Hits:

[VHDL-FPGA-Verilog] xor

Description: this the vhdl code for exor gate using dataflow modelling-this is the vhdl code for exor gate using dataflow modelling
Platform: | Size: 8192 | Author: nagaraju | Hits:

[VHDL-FPGA-Verilog] xor

Description: implementation of XOR gate in VHDL with rtl view and simulations
Platform: | Size: 23552 | Author: roby | Hits:

[VHDL-FPGA-Verilog] xors_1

Description: this xor gate in vhdl run under active hdl-this is xor gate in vhdl run under active hdl
Platform: | Size: 12288 | Author: sag | Hits:

[Software Engineering] vhdl

Description: library ieee use ieee.std_logic_1164.all entity decoder is port (clk:in std_logic clr:in std_logic data_in:in std_logic --待解码信元输入端； data_out:out std_logic) --解码信元输出端； end decoder architecture behave of decoder is component dff2 --上升沿D 触发器； port(d,clk,clr:in std_logic q:out std_logic) end component component xor2 --两输入异或门； port (a,b:in std_logic y:out std_logic) end component --一输入两输出电子开关； component switch21 port (clk,d,clr:in std_logic y:out std_logic) end component component emendation --校正电路； port (d,clk,clr:in std_logic y:out std_logic) end component signal s1,s2,s3,s4,s5: std_logic begin u0:switch21 port map (data_in ,clk,clr,s1,s2) u1: emendation port map (s1,clk,clr,s3) u2: dff2 port map (s2,clk,clr,s4) u3: xor2 port map (s3,s4,s5) data_out <= s5 end -library ieee use ieee.std_logic_1164.all entity decoder is port (clk: in std_logic clr: in std_logic data_in: in std_logic - be decoded cell inputs data_out: out std_logic) - Decoding Cell output end decoder architecture behave of decoder is component dff2- edge D flip-flop port (d, clk, clr: in std_logic q: out std_logic) end component component xor2- two input XOR gate port (a, b: in std_logic y: out std_logic) end component - an input two output electronic switch component switch21 port (clk, d, clr: in std_logic y: out std_logic) end component component emendation- correction circuit port (d, clk, clr: in std_logic y: out std_logic) end component signal s1, s2, s3, s4, s5: std_logic begin u0: switch21 port map (data_in, clk , clr, s1, s2) u1: emendation port map (s1, clk, clr, s3) u2: dff2 port map (s2, clk, clr, s4) u3: xor2 port map (s3, s4, s5) data_out < = s5 end
Platform: | Size: 377856 | Author: 刘轩赫 | Hits:

[Hook api] XOR

Description: IT IS A GOOD CODE IN VHDL FOR XOR GATE
Platform: | Size: 230400 | Author: guru | Hits:

[VHDL-FPGA-Verilog] VHDL-projects

Description: I have simple five VHDL projects. I use FPGA Spartan3A family board with XC3S50A FPGA chip. This project was created in Xilinx ISE Design Suite version (13.2).It contains divider,XOR blocks, counters, moore automat and more.
Platform: | Size: 1505280 | Author: Jaroslav | Hits:
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