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[USB develop] usb_phy

Description: usb接口协议。It was tested with a USB 1.1 core I have written on a XESS XCV800 board with a a Philips PDIUSBP11A transceiver. -usb interface protocol. It was tested with a USB 1.1 core I have written ona XESS XCV800 board with aa Philips PDIUSBP11A transceiver.
Platform: | Size: 11264 | Author: 颜新卉 | Hits:

[VHDL-FPGA-Verilog] aa

Description: xilinx环境下开发vhdl语言串行接口设计-Xilinx VHDL language development environment serial interface design
Platform: | Size: 219136 | Author: wang | Hits:

[VHDL-FPGA-Verilog] daima

Description: 用VHDL语言设计一个8位加法器： 在八位加法器代码一中：加法器是由两个4位二进制加法器U1和U2组成的8位加法器逻辑电路，其中U1用来装载8位加法器中两个加数的低4位，而U2则用来装载高4位。在设计4位加法器时，定义输入信号量CIN、A、B以及输出信号量S、Cout。定义信号量SINT/AA/BB，将加数A和0并置后赋给AA，加数B和0并置后赋给BB，形成5位二进制数，这是为在做加法时发生溢出所做的处理，然后将加数AA与BB以及进位Cin相加赋给SINT，并将SINT的低4位赋给加数和S输出，同时将SINT最高位传送给Cout输出。在设计8位加法器时，定义一个信号量CARRY，将4位加法器U1的COUT赋给CARRY，再将CARRY的值赋给4位加法器U2的进位位Cin，8位加法器的高4位和低4位分别来自于4位加法器U2和U1。 而在八位加法器代码二中：8位加法器的设计不使用底层文件，直接设计为8位与8位的相加，该种方法在设计上更为简洁。在实验硬件连接上，可以使用LED七段数码管显示所得结果，使结果显示更为清晰明了。 -With VHDL language design 8 accumulators: in eight accumulator codes in one: The accumulator is 8 accumulator logic circuit which is composed of two 4 binary system accumulator U1 and U2, U1 uses for to load in 8 accumulators two addend low 4, but U2 uses for to load high 4. When designs 4 accumulators, the definition input signal measures CIN, A, B as well as the output signal measures S, Cout. The definition signal measures SINT/AA/BB, after addend A and 0 juxtapositions, bestows on for AA, after addend B and 0 juxtapositions, bestows on for BB, forms 5 binary system number, this is for when does the addition has processing which the overflow does, then as well as carries Cin addend AA and BB to levy additional taxes for SINT, and the SINT low 4 taxes for the addend and the S output, simultaneously transmits the SINT highest order to the Cout output. When designs 8 accumulators, defines a signal to measure CARRY, bestows on 4 accumulator U1 COUT for CARRY, bestows on again the CARRY
Platform: | Size: 9216 | Author: SAM | Hits:

[Documents] aa

Description: 基于模糊神经网络的自适应预失真功放。DPD功放模型的研究。-Based on fuzzy neural network adaptive predistortion power amplifier. DPD amplifier modeling.
Platform: | Size: 174080 | Author: jack | Hits:

[source in ebook] counter

Description: 计数器VHDL,可以用modersim仿真-it is a a a a aa a a a a a a counter VHDL
Platform: | Size: 1024 | Author: 张欣 | Hits:

[Other] aa

Description: 数字频率计VHDL程序-Digital frequency meter VHDL program
Platform: | Size: 2048 | Author: 黄濡 | Hits:

[VHDL-FPGA-Verilog] aa

Description: 洗衣机控制vhdl，洗涤、漂洗和脱水，每个功能持续的时间分别为20秒、15秒和10秒-vhdl
Platform: | Size: 12288 | Author: li henan | Hits:

[VHDL-FPGA-Verilog] aa

Description: 这个程序就是序列检测器的vhdl实现，真麻烦啊-This program is the sequence detector vhdl achieve real trouble
Platform: | Size: 1024 | Author: zhangzhen | Hits:

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