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Description: 本设计为32位数字相位累加器，门级描述的Verilog代码。其中，acc32bit.v为顶层文件，full_add1.v为一位全加器的门级描述模块，flop.v为触发器的门级描述模块。-The design for the 32-bit digital phase accumulator, gate-level description of the Verilog code. Which, acc32bit.v as top-level file, full_add1.v as a full adder gate-level description module, flop.v to trigger the gate-level description of the module.
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Size: 755712 |
Author: 吴亮 |
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