Description: The design for the 32-bit digital phase accumulator, gate-level description of the Verilog code. Which, acc32bit.v as top-level file, full_add1.v as a full adder gate-level description module, flop.v to trigger the gate-level description of the module.
- [ddssinegeneratorcode.Rar] - described dds direct digital frequency s
- [FPGA_DDS] - the DDS is depend on the fpga ,and we de
- [xiangweileijiaqi] - Phase accumulator, digital frequency syn
- [vhdl] - Application of the design described in V
- [cla20_n] - Verilog 20 bit accumulator using water i
- [SG_FPGA] - Electronic Design Competition 2006, seco
File list (Check if you may need any files):
acc32bit\acc32bit.asm.rpt
........\acc32bit.done
........\acc32bit.fit.rpt
........\acc32bit.fit.smsg
........\acc32bit.fit.summary
........\acc32bit.flow.rpt
........\acc32bit.map.rpt
........\acc32bit.map.smsg
........\acc32bit.map.summary
........\acc32bit.pin
........\acc32bit.pof
........\acc32bit.qpf
........\acc32bit.qsf
........\acc32bit.qws
........\acc32bit.sim.rpt
........\acc32bit.sof
........\acc32bit.tan.rpt
........\acc32bit.tan.summary
........\acc32bit.v
........\acc32bit.v.bak
........\acc32bit.vwf
........\db\acc32bit.asm.qmsg
........\..\acc32bit.asm_labs.ddb
........\..\acc32bit.atom.rvd
........\..\acc32bit.cbx.xml
........\..\acc32bit.cmp.bpm
........\..\acc32bit.cmp.cdb
........\..\acc32bit.cmp.ecobp
........\..\acc32bit.cmp.hdb
........\..\acc32bit.cmp.logdb
........\..\acc32bit.cmp.rdb
........\..\acc32bit.cmp.tdb
........\..\acc32bit.cmp0.ddb
........\..\acc32bit.db_info
........\..\acc32bit.eco.cdb
........\..\acc32bit.eds_overflow
........\..\acc32bit.fit.qmsg
........\..\acc32bit.fnsim.cdb
........\..\acc32bit.fnsim.hdb
........\..\acc32bit.fnsim.qmsg
........\..\acc32bit.hier_info
........\..\acc32bit.hif
........\..\acc32bit.map.bpm
........\..\acc32bit.map.cdb
........\..\acc32bit.map.ecobp
........\..\acc32bit.map.hdb
........\..\acc32bit.map.logdb
........\..\acc32bit.map.qmsg
........\..\acc32bit.map_bb.cdb
........\..\acc32bit.map_bb.hdb
........\..\acc32bit.map_bb.hdbx
........\..\acc32bit.map_bb.logdb
........\..\acc32bit.pre_map.cdb
........\..\acc32bit.pre_map.hdb
........\..\acc32bit.psp
........\..\acc32bit.root_partition.cmp.atm
........\..\acc32bit.root_partition.cmp.dfp
........\..\acc32bit.root_partition.cmp.hdbx
........\..\acc32bit.root_partition.cmp.logdb
........\..\acc32bit.root_partition.cmp.rcf
........\..\acc32bit.root_partition.map.atm
........\..\acc32bit.root_partition.map.hdbx
........\..\acc32bit.root_partition.map.info
........\..\acc32bit.rpp.qmsg
........\..\acc32bit.rtlv.hdb
........\..\acc32bit.rtlv_sg.cdb
........\..\acc32bit.rtlv_sg_swap.cdb
........\..\acc32bit.sgate.rvd
........\..\acc32bit.sgate_sm.rvd
........\..\acc32bit.sgdiff.cdb
........\..\acc32bit.sgdiff.hdb
........\..\acc32bit.signalprobe.cdb
........\..\acc32bit.sim.cvwf
........\..\acc32bit.sim.hdb
........\..\acc32bit.sim.qmsg
........\..\acc32bit.sim.rdb
........\..\acc32bit.sld_design_entry.sci
........\..\acc32bit.sld_design_entry_dsc.sci
........\..\acc32bit.syn_hier_info
........\..\acc32bit.tan.qmsg
........\..\acc32bit.tis_db_list.ddb
........\..\acc32bit.tmw_info
........\..\prev_cmp_acc32bit.asm.qmsg
........\..\prev_cmp_acc32bit.fit.qmsg
........\..\prev_cmp_acc32bit.map.qmsg
........\..\prev_cmp_acc32bit.qmsg
........\..\prev_cmp_acc32bit.sim.qmsg
........\..\prev_cmp_acc32bit.tan.qmsg
........\..\wed.wsf
........\flop.v
........\flop.v.bak
........\full_add1.v
........\full_add1.v.bak
........\db
acc32bit
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