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[Other] fpdiv_vhdl四位除法器

Description: fpdiv_vhdl四位除法器 -- DESCRIPTION : Signed divider -- A (A) input width : 4 -- B (B) input width : 4 -- Q (data_out) output width : 4 -- DIV_BY_0 (DIVz) output active : high-fpdiv_vhdl four divider-- DESCRIPTION : Signed divider-- A (A) input width : 4-- B (B) input width : 4-- Q (data_out) output width : 4-- DIV_BY_0 (DIVz) output active : high
Platform: | Size: 1024 | Author: 张洪 | Hits:

[Communication] crc上传程序

Description: 写CRC编解码程序时，整理的文件，压缩文件既有理论说明，也有源代码。源代码格式用C,VHDL,Verilog。-write CRC codec procedures, collating documents, compressed files both theoretical statements, and the active code. Source code format C, VHDL, Verilog.
Platform: | Size: 706560 | Author: cdl | Hits:

[VHDL-FPGA-Verilog] vhdl_8cpu

Description: VHDL实现简单的8位CPU doc文件上有源代码-VHDL simple eight CPU doc documents Active code
Platform: | Size: 52224 | Author: 紫蓝 | Hits:

[VHDL-FPGA-Verilog] 8b_10b

Description: vhdl编写，8b—10b 编解码器设计 Encoder: 8b/10b Encoder (file: 8b10b_enc.vhd) Synchronous clocked inputs (latched on each clock rising edge) 8-bit parallel unencoded data input KI input selects data or control encoding Asynchronous active high reset initializes all logic Encoded data output 10-bit parallel encoded output valid 1 clock later Decoder: 8b/10b Decoder (file: 8b10b_dec.vhd) Synchronous clocked inputs (latched on each clock rising edge) 10-bit parallel encoded data input Asynchronous active high reset initializes all logic Decoded data, disparity and KO outputs 8-bit parallel unencoded output valid 1 clock later -VHDL prepared, 8b-10b codec design Encoder: 8b/10b Encoder (file: 8b10b_enc.vhd) Synchronous clocked inputs (latched on each clock rising edge) 8-bit parallel unencoded data input KI input selects data or control encoding Asynchronous active high reset initializes all logic Encoded data output 10-bit parallel encoded output valid 1 clock later Decoder: 8b/10b Decoder (file: 8b10b_dec.vhd) Synchronous clocked inputs (latched on each clock rising edge) 10-bit parallel encoded data input Asynchronous active high reset initializes all logic Decoded data, disparity and KO outputs 8-bit parallel unencoded output valid 1 clock later
Platform: | Size: 72704 | Author: 聂样 | Hits:

[VHDL-FPGA-Verilog] shift_register

Description: -- DESCRIPTION : Shift register -- Type : univ -- Width : 4 -- Shift direction: right/left (right active high) -- -- CLK active : high -- CLR active : high -- CLR type : synchronous -- SET active : high -- SET type : synchronous -- LOAD active : high -- CE active : high -- SERIAL input : SI-- DESCRIPTION: Shift register- Type: univ- Width: 4- Shift direction: right/left (right active high )---- CLK active: high- CLR active: high- CLR type: synchronous-- SET active: high- SET type: synchronous- LOAD active: high- CE active: high- SERIAL input: SI
Platform: | Size: 1024 | Author: sanshanchuns | Hits:

[VHDL-FPGA-Verilog] memory_example

Description: This simple example allows you to get familiar with Active-HDL s Memory Viewer.
Platform: | Size: 10240 | Author: leiyu | Hits:

[VHDL-FPGA-Verilog] 138

Description: 用vhdl 语言实现138译码器，用vhdl 语言实现138译码器，-vhdl vhdl vhdl vhdl vhdl vhdl vhdl vhdl vhdl vhdl vhdl vhdl vhdl vhdl vhdl vhdl vhdl
Platform: | Size: 92160 | Author: 洪烨 | Hits:

[OS Develop] program

Description: 设计实现4bit FIFO, 数据深度为8， 产生满， 空状态标志-The diagram of FIFO is shown in figure 1. The FIFO consists of two component: FIFO control logic and RAM. The control logic generates the address (ADD) and write enable (WE) to the RAM so that the first data word written into the RAM is also the first data word retrieved from the RAM. As shown in the Figure 1, the RAM is implemented to operate as a FIFO. The RAM is assumed to have separate data inputs and outputs, an N-bit address bus (ADD) and an active high write enable (WE). The inputs to FIFO/Stack include PUSH, POP, INIT (all active high) in addition to the rising edge triggered CLK input. The FIFO logic will not only supply the address and write enable to the RAM, but will also supply active high flags for FULL, EMPTY, NOPOP, and NOPUSH conditions.
Platform: | Size: 3072 | Author: shao | Hits:

[Driver Develop] PwmRefComp1

Description: active power meter for code vhdl is a pdf we can s-active power meter for code vhdl is a pdf we can see
Platform: | Size: 38912 | Author: luias | Hits:

[Other] vhdl

Description: 实现代码，A、B为输入、Y为输出，它们为8位向量。OE为输出使能，低电平有效。IE为输入锁存时能，上升沿有效。Ci为进位输入，Co为进位输出。 S0、S1、S2为运算逻辑选择输入： ，用vhdl语言编写，基于数字电路。-Implementation code, A, B input, Y the output, they are 8-bit vector. OE to output enable, active low. IE when the input latch, rising edge and effective. Ci for the Carry input, Co to carry out. S0, S1, S2 for the arithmetic logic selection input: using vhdl language, based on digital circuits.
Platform: | Size: 1024 | Author: youruo | Hits:

[VHDL-FPGA-Verilog] SRAM_Control

Description: VHDL Code for SRAM Control (Synthesized with Synplify-Pro, Active-HDL Simulation)
Platform: | Size: 82944 | Author: DongHee Kim | Hits:

[Other] VHDL

Description: The presention of ACTIVE HDL which will be used for implementation of reconfigurable structure with VHDL-The presention of ACTIVE HDL which will be used for implementation of reconfigurable structure with VHDL
Platform: | Size: 5150720 | Author: Silvana | Hits:

[VHDL-FPGA-Verilog] finalcoursework

Description: 用VHDL代码写的模拟微处理器核程序，有计算模块和register file 等模块，并包含测试程序，调试程序 ACTIVE HDL-Simulation with the VHDL code is written in the microprocessor core procedures, such as computing modules, and register file module, and includes test program, the debugger ACTIVE HDL
Platform: | Size: 43008 | Author: 三木 | Hits:

[SCM] Bintograyconverter

Description: Bin to gray converter Input (DATA_IN) width : 4 Enable (EN) active : high Bin to Bcd converter Input (data_in) width : 4 Output (data_out) width : 8 Enable (EN) active : high -Bin to gray converter -- Input (DATA_IN) width : 4 -- Enable (EN) active : high Bin to Bcd converter Input (data_in) width : 4 Output (data_out) width : 8 Enable (EN) active : high
Platform: | Size: 1024 | Author: haodiangei | Hits:

[VHDL-FPGA-Verilog] active-hdl-vhdl-code

Description: this vhdl source code for multiplexer,half adder,full adder,counter etc. for using in ACTIVE HDL and other vlsi softwares.-this is vhdl source code for multiplexer,half adder,full adder,counter etc. for using in ACTIVE HDL and other vlsi softwares.
Platform: | Size: 1024 | Author: anmol | Hits:

[VHDL-FPGA-Verilog] Qdaqi

Description: 基于VHDL语言 实现八路抢答器 有源时钟48mhz 功能为任意按键按下屏蔽其它按键输入-VHDL language based on the active clock 48mhz eight Responder function to any button is pressed the other key input screen
Platform: | Size: 287744 | Author: 张帝 | Hits:

[VHDL-FPGA-Verilog] Design_74LS138

Description: 利用Active-VHDL 来仿真测试74LS138 译码器，74LS138 译码器是3 线-8 线译 码器。-To the use of Active-VHDL simulation test 74LS138 decoder, 74LS138 decoder is a 3-wire-8 line decoder.
Platform: | Size: 11264 | Author: stronger | Hits:

[VHDL-FPGA-Verilog] VHDL

Description: An active methodology for teaching electronic systems design
Platform: | Size: 10209280 | Author: 刘洋 | Hits:

[Other] jingzhen

Description: 将6mhz有源晶振分频的分频器件vhdl程序-The active crystal 6mhz divide divider pieces vhdl program
Platform: | Size: 9216 | Author: tony | Hits:

[MultiLanguage] PWM

Description: PWM VHDL spartan 3e active vhdl nexys2
Platform: | Size: 8192 | Author: Tcko | Hits:
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