Search - ad vhdl

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[VHDL-FPGA-Verilog] vhdl程序例子 DL : 0: vhdl程序源代码，包括Combinational Logic Counters Shift Registers Memory State Machines Registers Systems ADC and DAC Arithmetic等-VHDL source code, including Combinational Logic Counters Shift Registers State Machines Registers Memory Systems ADC and DAC Arithmetic etc.
Update : 2025-02-17 Size : 165kb Publisher : 王力
[Embeded-SCM Develop] 1549 DL : 0: ad采集程序，已经经过仿真验证，能够直接应用-ad collection procedure has been verified through simulation, to the direct application
Update : 2025-02-17 Size : 1kb Publisher : xuying
[VHDL-FPGA-Verilog] arith_lib_cadence DL : 0: Cadence的VHDL运算库包，实现求方根，平方你是不是以前不知道怎么弄．哈哈．-Cadence VHDL Operational the package, seeking to achieve root, You are not square did not know how get. Ha ha.
Update : 2025-02-17 Size : 80kb Publisher : 喻袁洲
[VHDL-FPGA-Verilog] vhdl_ad0809_arm DL : 0: 本程序是用VHDL语言写的，包括AD0809，双口RAM等程序。已经调试过-this program is written in VHDL, including the AD0809, dual-port RAM, and other procedures. Debugging has been too
Update : 2025-02-17 Size : 4kb Publisher : lm
[SCM] 0809conventorvhdl DL : 0: 1.AD0809转换器的vhdl实现 2.用状态机来实现不同状态的动态切换，思路明晰简单实现。 3.内含注释，易于修改和理解 4.对数码管的动态扫描,显示 -1.AD0809 converters to achieve the two vhdl. Using the state machine to achieve the different states of dynamic switching thinking, clarity simple to achieve. 3. Notes intron and easy to understand and 4. Digital control of the dynamic scan showed
Update : 2025-02-17 Size : 1kb Publisher : 方周
[VHDL-FPGA-Verilog] ADC0809VHDL DL : 0: VHDL语言编写的程序，实现控制ADC0809的工作 -VHDL prepared by the procedures, the control Connection between ADC 0809
Update : 2025-02-17 Size : 4kb Publisher : wang
[VHDL-FPGA-Verilog] adc0809 DL : 0: VHDL编写的ADC0809 控制器，经过验证没有错误-VHDL prepared ADC0809 controller, no errors verified
Update : 2025-02-17 Size : 1kb Publisher : 王攀
[Software Engineering] chengxu DL : 0: ad转换的程序，c8051f021老程序，18B20测温00，抢答器程序，pwm_pac.c。-ad conversion process, c8051f021 old procedures, 18B20 temperature 00, Answer program, pwm_pac.c.
Update : 2025-02-17 Size : 2.92mb Publisher : Liang
[VHDL-FPGA-Verilog] adc DL : 0: Analog-to-Digital Converter，VHDL code-Analog-to-Digital Converter, VHDL code
Update : 2025-02-17 Size : 14kb Publisher : leigh lee
[Embeded-SCM Develop] ADS8361 DL : 0: TI公司的AD8361的VHDL控制程序，可实现CPLD的采集。-TI s AD8361 the VHDL control procedures, the acquisition can be realized CPLD.
Update : 2025-02-17 Size : 1kb Publisher : 祝箭
[VHDL-FPGA-Verilog] ads7844 DL : 0: 本源码介绍了ADS7844 AD转换芯片的VHDL控制器。-The source of the introduction ADS7844 AD conversion of the VHDL controller chip.
Update : 2025-02-17 Size : 1.32mb Publisher : 周生
[VHDL-FPGA-Verilog] AD9826.vhd DL : 0: 驱动AD9826的VHDL程序，经测试可以成功驱动-AD9826 driver of VHDL procedures, have been tested successfully drive
Update : 2025-02-17 Size : 1kb Publisher : wuchao
[VHDL-FPGA-Verilog] xapp355 DL : 0: Serial ADC Interface write in VHDL based on xilinx cpld
Update : 2025-02-17 Size : 33kb Publisher : jiang
[File Format] ram_da DL : 0: 将AD转换得到的八位数据存入RAM，存1000个点，然后通过串行DA读出，DA芯片为TLV5638,AD芯片为tlc0820ac，RAM为FM25L16-AD conversion will be the eight data into RAM, keep 1000 points, and then read out through the DA serial, DA chips for the TLV5638, AD chips for tlc0820ac, RAM for FM25L16
Update : 2025-02-17 Size : 635kb Publisher : 王力
[Other] a2d2 DL : 0: ad取样，经由cpld处理，存入ram 1000点并由串行的da进行还原-ad sampling, by the CPLD deal, deposited by the serial ram 1000 points to restore the da
Update : 2025-02-17 Size : 176kb Publisher :
[VHDL-FPGA-Verilog] ADC0809_VHDL_ctrl DL : 0: VHDL控制ADC0809芯片，实现AD转化及采集后数据的读写。-VHDL control ADC0809 chip realize after AD conversion and acquisition of reading and writing data.
Update : 2025-02-17 Size : 4kb Publisher : zhou129
[Algorithm] AD DL : 0: 用于AD转换的，is very good for you -For AD conversion, is very good for you
Update : 2025-02-17 Size : 482kb Publisher : fei
[Compress-Decompress algrithms] STCApplication DL : 0: sTC系列单片机内部AD的应用 STC89LE52AD、54AD、58AD、516AD这几款89系列的STC单片机内部自带有8路8位的AD转换器，分布在P1口的8位上，当时钟在40MHz以下时，每17个机器周期可完成一次AD转换。 -STC series single-chip internal AD Application STC89LE52AD, 54AD, 58AD, 516AD that several 89 series of STC has its own single-chip 8-way internal 8-bit AD converter, the distribution of P1 at the mouth of 8 on, when the bell At 40MHz below, every 17 machine cycles to be completed by an AD converter.
Update : 2025-02-17 Size : 2kb Publisher : 力伟
[VHDL-FPGA-Verilog] AD-Based_on_FPGA DL : 0: 使用VHDL语言编写的A/D转换程序，可在FPGA平台使用-VHDL language used A/D conversion process can be used in the FPGA platform
Update : 2025-02-17 Size : 57kb Publisher : 东风
[VHDL-FPGA-Verilog] AD DL : 0: 用硬件语言VHDL编写AD采集系统，经过仿真结果正确-Hardware language VHDL with the preparation of AD acquisition system, after a simulation result is correct
Update : 2025-02-17 Size : 156kb Publisher : 王岩嵩

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