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[matlab] DPLL1lp

Description: 频带数字通信中，频带一阶锁相环simulink模型-band digital communications, a frequency band PLL Simulink model
Platform: | Size: 8192 | Author: rossi | Hits:

[VHDL-FPGA-Verilog] adpll

Description: 全数字锁相环 功能与74297相同 提供参数配置-All-digital phase-locked loop function and to provide parameters to configure the same 74,297
Platform: | Size: 2048 | Author: lizhizhou | Hits:

[VHDL-FPGA-Verilog] a

Description: ADPLL of high level phase locked loop
Platform: | Size: 1471488 | Author: bc | Hits:

[Other] b

Description: A high-speed variable phase accumulator for an ADPLL architecture
Platform: | Size: 287744 | Author: bc | Hits:

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