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[Crack Hack] 高级加密算法

Description: AES加密和解密源码！-AES encryption and decryption source!
Platform: | Size: 101376 | Author: 古月 | Hits:

[Crack Hack] AES算法完整源码

Description: AES算法完整源码-AES complete source
Platform: | Size: 225280 | Author: 天上人间 | Hits:

[Crack Hack] aes_encrypt

Description: AES加密软件，用于加密当前文本框中的内容。使用的是美国国家标准（也被ISO所采纳）最新加密算法AES。-AES encryption software, encryption for the current contents of the text box. The use of the American National Standards (also adopted by the ISO) the latest encryption algorithm AES.
Platform: | Size: 216064 | Author: | Hits:

[VHDL-FPGA-Verilog] AEScoremodules

Description: AES decoder aes_dec.vhdl AES encoder aes_enc.vhdl Package used by rest of design aes_pkg.vhdl Key Expansion component for AES encoder and decoder key_expansion.vhdl -AES AES encoder decoder aes_dec.vhdl aes_ enc.vhdl Package used by rest of design aes_pkg . vhdl Key Expansion component for a AES encoder nd decoder key_expansion.vhdl
Platform: | Size: 10240 | Author: 许茹芸 | Hits:

[Other] EMCRYPTCHIPFORFPGA

Description: 基于FPGA加密芯片设计论文（AES和DES算法）-FPGA-based encryption chip design thesis (AES and DES algorithm)
Platform: | Size: 1068032 | Author: David | Hits:

[Crack Hack] aes

Description: aes加密算法实现，经过FPGA验证的！-aes encryption algorithm, after FPGA validation!
Platform: | Size: 6144 | Author: guochao | Hits:

[Crack Hack] AES

Description: AES算法的verilog代码，即AES算法IP核-ip core for AES
Platform: | Size: 13312 | Author: JJ | Hits:

[VHDL-FPGA-Verilog] aes

Description: vhdl implementation of the AES encryption algorithm
Platform: | Size: 244736 | Author: hesham | Hits:

[VHDL-FPGA-Verilog] aes

Description: 实现了AES在赛灵思器件上的加密程序 我已经调试过完全正确-Xilinx achieved in AES encryption device debugging process I have been absolutely correct
Platform: | Size: 4096 | Author: wangrui | Hits:

[Crack Hack] freehdl-0.0.6.tar

Description: inplementation of AES vhdl The use of a list of law, VHDL language based polynomial-based finite field multiplier, for the AES algorithm
Platform: | Size: 1391616 | Author: tarik | Hits:

[Algorithm] AES

Description: This the source code of AES algorithm which is used in network security.-This is the source code of AES algorithm which is used in network security.
Platform: | Size: 10240 | Author: Krupesh | Hits:

[VHDL-FPGA-Verilog] aes

Description: 高级加密标准AES的FPGA实现，支持128，256密钥长度格式-Advanced Encryption Standard AES, FPGA implementation to support 128,256 key length format
Platform: | Size: 87040 | Author: dinxj | Hits:

[VHDL-FPGA-Verilog] AES!

Description: AES algorithm very good code tested in xilinx ise tool
Platform: | Size: 9216 | Author: hr | Hits:

[VHDL-FPGA-Verilog] aes

Description: aes的加密解密算法的源代码以及测试源代码和仿真结果图-aes encryption decryption algorithm source code and test source code and simulation results map
Platform: | Size: 2973696 | Author: cong | Hits:

[VHDL-FPGA-Verilog] AES

Description: AES implementation in VHDL@!
Platform: | Size: 521216 | Author: manishrb | Hits:

[VHDL-FPGA-Verilog] aes

Description: verilog实现的AES-128加解密程序，FPGA验证通过-verilog implementation of AES-128 encryption and decryption process, FPGA verification through
Platform: | Size: 7168 | Author: xie | Hits:

[Crack Hack] AES

Description: 详细描述了AES加密算法的过程及S盒变换，用VHDL语言描述，通俗易懂-AES encryption algorithm is described in detail the process and transform S box, with the VHDL language to describe, easy to understand
Platform: | Size: 559104 | Author: 韩颖 | Hits:

[VHDL-FPGA-Verilog] aes-vhdl

Description: 使用vhdl语言实现aes（rijndael 算法），程序整体封装成为一个package，方便调用-Using vhdl language aes (rijndael algorithm), the program as a whole package as a package, easy call
Platform: | Size: 7168 | Author: Bruce Lee | Hits:

[VHDL-FPGA-Verilog] aes-vhdl

Description: this file contains vhdl code for aes
Platform: | Size: 119808 | Author: baby | Hits:

[VHDL-FPGA-Verilog] aes-master

Description: aes master by vhdl code and decode
Platform: | Size: 68608 | Author: Nguyen Nam | Hits:
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