Search - aes algorithm in fpga

Search - aes algorithm in fpga - List

[Other] EMCRYPTCHIPFORFPGA DL : 0: 基于FPGA加密芯片设计论文（AES和DES算法）-FPGA-based encryption chip design thesis (AES and DES algorithm)
Update : 2025-02-17 Size : 1.02mb Publisher : David
[Crack Hack] aes_encryption DL : 0: aes加密算法的VHDL代码实现，在FPGA芯片上调试过-aes encryption algorithm realize the VHDL code in FPGA chips upward tried
Update : 2025-02-17 Size : 6kb Publisher : stym_001
[Software Engineering] AES DL : 0: 基于fpga的AES高速实现，介绍了算法实现的过程，仿真结果。-FPGA-based high-speed realization of the AES, introduced the process of algorithm, the simulation results.
Update : 2025-02-17 Size : 1.35mb Publisher : 王旺
[Crack Hack] aes DL : 0: aes加密算法实现，经过FPGA验证的！-aes encryption algorithm, after FPGA validation!
Update : 2025-02-17 Size : 6kb Publisher : guochao
[Crack Hack] khalil2006_true_random_number_generator DL : 0: a true random number generator (TRNG) in hardware which is targeted for FPGA-based crypto embedded systems. All crypto protocols require the generation and use of secret values that must be unknown to attackers.Random number generators (RNG) are required to generate public/private key pairs for asymmetric algorithm such as RSA and symmetric algorithm such as AES.
Update : 2025-02-17 Size : 409kb Publisher : Hassan Abdelaziz
[Crack Hack] systemcaes_latest.tar DL : 0: 高级加密标准aes加密算法用fpga实现的Verilog源代码。-Advanced encryption standard aes encryption algorithm using fpga implementation Verilog source code.
Update : 2025-02-17 Size : 82kb Publisher : lxc
[VHDL-FPGA-Verilog] aescore DL : 0: 基于FPGA的AES算法实现的VERILOG源代码，对于信息安全专业研究AES算法的硬件实现很有用-FPGA-based AES algorithm implementation VERILOG source code, for the information security professional research of the hardware implementation of AES algorithm is useful
Update : 2025-02-17 Size : 191kb Publisher : 李华
[Crack Hack] AESFPGA DL : 0: 论文介绍了AES算法在FPGA上的实现功能，对AES算法过程进行了优化。-This paper introduces the AES algorithm in FPGA implementation function of the AES algorithm to optimize the process.
Update : 2025-02-17 Size : 630kb Publisher : 朱丽丽
[Crack Hack] AES-based-on-FPGA-jiami DL : 0: 该模块是基于FPGA的AES加密算法实现的Verilog代码，包含一个顶层文件和两个调用模块，最高误差在15ns-This module is the AES encryption algorithm FPGA based on the Verilog code, contains a top-level files and two call module, the maximum error in 15ns
Update : 2025-02-17 Size : 14.25mb Publisher : 庄德坤
[File Format] AES-FPGA DL : 0: 本文介绍了AES加密算法通过不同的功能结构的FPGA实现，语言背景为VHDL-This paper details Implementation of the Encryption algorithm AES under VHDL language In FPGA by using different architecture of mixcolumn. We then review this research investigates the AES algorithm in FPGA and the Very High Speed Integrated Circuit Hardware Description language (VHDL). Altera Quartus II software is used for simulation and optimization of the synthesizable VHDL code. The set of transformations of both Encryptions and decryption are simulated using an iterative design approach in order to optimize the hardware consumption. Altera Cyclone III Family devices are utilized for hardware uation.
Update : 2025-02-17 Size : 187kb Publisher : Eric
[VHDL-FPGA-Verilog] 20161227_sf DL : 0: AES加密算法中的列混合模块的FPGA实现源代码，采用Verillog语言，在软件Quartus II上综合-AES encryption algorithm in the FPGA column hybrid module implementation source code, using language Verillog integrated in the Quartus II software
Update : 2025-02-17 Size : 129kb Publisher : 柳广兴