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[VHDL-FPGA-Verilog] aes

Description: 实现了AES在赛灵思器件上的加密程序 我已经调试过完全正确-Xilinx achieved in AES encryption device debugging process I have been absolutely correct
Platform: | Size: 4096 | Author: wangrui | Hits:

[ARM-PowerPC-ColdFire-MIPS] 2440Program

Description: ARM 2440的操作系统与IPcore 设计-ARM 2440 operation system and IPcore
Platform: | Size: 496640 | Author: 李江 | Hits:

[Crack Hack] aes

Description: 其程序是用xilinx环境下编写的，风格是Verilog，请大家提意见。-The program is written using xilinx environment, style Verilog, please comments.
Platform: | Size: 3072 | Author: 郝志刚 | Hits:

[VHDL-FPGA-Verilog] AES!

Description: AES algorithm very good code tested in xilinx ise tool
Platform: | Size: 9216 | Author: hr | Hits:

[VHDL-FPGA-Verilog] 256fft

Description:
Platform: | Size: 209920 | Author: Nagendran | Hits:

[VHDL-FPGA-Verilog] xapp514_aes3-audio

Description: DVB数字音频接口(AESEBU)encoder源码,包括VHDL和VERILOG,基于XILINX FPGA,已验证.-AES-EBU interface,VHDL,VERILOG
Platform: | Size: 4483072 | Author: dcshl | Hits:

[VHDL-FPGA-Verilog] AES256-XILINX10.1

Description: 用XILINX公司提供的NetFPGA板卡并结合软件Xilinx10.1进行系统设计，采用硬件描述语言Verilog实现了 AES-256加密算法。-Provided by XILINX board combined with software Xilinx10.1 NetFPGA system design, using Verilog hardware description language implementation of the AES-256 encryption algorithm.
Platform: | Size: 5120 | Author: yuanying | Hits:

[VHDL-FPGA-Verilog] VHDL_AES_ZigBee

Description: 用VHDL实现的ZigBee模块控制算法以及AES加密算法，用于Xilinx的FPGA!-With the realization of VHDL ZigBee module control algorithm and AES encryption algorithms for Xilinx FPGA!
Platform: | Size: 208896 | Author: 风之子 | Hits:

[Compress-Decompress algrithms] aes_fifo_interface

Description: aes to fsl with xilinx fpga
Platform: | Size: 1024 | Author: valter | Hits:

[VHDL-FPGA-Verilog] aes_fsl_interface

Description: aes to fsl with xilinx fpga
Platform: | Size: 1024 | Author: valter | Hits:

[VHDL-FPGA-Verilog] AESzuihou

Description: 在赛灵思软件ISE上实现的ＡＥＳ加解密算法，并且在ＭＯＤＥＬＳＩＭ上仿真。希望对你有所帮助-The Xilinx software ISE AES encryption and decryption algorithms, and simulation MODELSIM on. I hope for your help
Platform: | Size: 80896 | Author: 杨俊明 | Hits:

[Other] ALTERA

Description: we are in this file about altera fpga xilinx communication syaterm toolbox for design and system requirements
Platform: | Size: 324608 | Author: ghorbanii | Hits:

[VHDL-FPGA-Verilog] Verilog

Description: aes digital audio interface from xilinx
Platform: | Size: 49152 | Author: SiamackBM | Hits:

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