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[Crack Hack] aes_core DL : 0: AES高级加密算法的verilog语言实现。同时附有AES协议的pdf文档，和此代码的测试程序，可作为一个IP核直接使用，可减少开发人员的设计时间。-AES Advanced Encryption Algorithm Verilog language. While the agreement with AES pdf documents, and that this code of the test procedure can be used as an IP core direct use, developers can reduce design time.
Update : 2008-10-13 Size : 77.92kb Publisher : 崔崔
[Com Port] vim_session_vim DL : 0: This a state-machine driven rs232 serial port interface to aes_core-This a state-driven machine rs232 seria l port interface to aes_core
Update : 2008-10-13 Size : 2.11kb Publisher : weixing
[Crack Hack] aes_core DL : 0: Verilog实现AES加密算法密码模块作为安全保密系统的重要组成部分，其核心任务就是加密数据。分组密码算法AES以其高效率、低开销、实现简单等特点目前被广泛应用于密码模块的研制中。密码模块一般被设计成外接在主机串口或并口的一个硬件设备或是一块插卡，具有速度快，低时延的特点。而从整体发展趋势来看，嵌入式密码模块由于灵活，适用于多种用户终端、通信设备和武器平台，将会得到更加广泛的应用
Update : 2008-10-13 Size : 77.77kb Publisher : yuansuchun
[Other resource] aes_core.tar DL : 0: AES的Verilog实现,用于加密的算法硬件实现!
Update : 2008-10-13 Size : 68.07kb Publisher : 刘志刚
[Crack Hack] aes_core DL : 0: AES高级加密算法的verilog语言实现。同时附有AES协议的pdf文档，和此代码的测试程序，可作为一个IP核直接使用，可减少开发人员的设计时间。-AES Advanced Encryption Algorithm Verilog language. While the agreement with AES pdf documents, and that this code of the test procedure can be used as an IP core direct use, developers can reduce design time.
Update : 2025-02-17 Size : 78kb Publisher :
[Com Port] vim_session_vim DL : 0: This a state-machine driven rs232 serial port interface to aes_core-This a state-driven machine rs232 seria l port interface to aes_core
Update : 2025-02-17 Size : 2kb Publisher : weixing
[Crack Hack] aes_core DL : 0: Verilog实现AES加密算法密码模块作为安全保密系统的重要组成部分，其核心任务就是加密数据。分组密码算法AES以其高效率、低开销、实现简单等特点目前被广泛应用于密码模块的研制中。密码模块一般被设计成外接在主机串口或并口的一个硬件设备或是一块插卡，具有速度快，低时延的特点。而从整体发展趋势来看，嵌入式密码模块由于灵活，适用于多种用户终端、通信设备和武器平台，将会得到更加广泛的应用-AES encryption algorithm realize Verilog module password security system as an important part of its core mission is to encrypt the data. AES block cipher algorithm for its high efficiency, low overhead, simple features such as the current password is widely used in research and development modules. Password modules are generally designed to host external serial or parallel port of a hardware device or a card with a high speed, low latency characteristics. From the overall development trend, the embedded code module as a result of flexible and applicable to many user terminals, communications equipment and weapons platforms, will be more widely applied
Update : 2025-02-17 Size : 78kb Publisher : yuansuchun
[VHDL-FPGA-Verilog] aes_core.tar DL : 0: AES的Verilog实现,用于加密的算法硬件实现!-AES realize the Verilog for hardware implementation of encryption algorithms!
Update : 2025-02-17 Size : 68kb Publisher : 刘志刚
[Software Engineering] AES DL : 0: 基于fpga的AES高速实现，介绍了算法实现的过程，仿真结果。-FPGA-based high-speed realization of the AES, introduced the process of algorithm, the simulation results.
Update : 2025-02-17 Size : 1.35mb Publisher : 王旺
[Crack Hack] aes_core DL : 0: aes_core verified verilog ip core-aes_core verified verilog ip core
Update : 2025-02-17 Size : 11kb Publisher : 邓婕
[VHDL-FPGA-Verilog] aes_core.tar DL : 0: 基于FPGA平台的256为AES加密IP核-FPGA-based platform for the AES encryption IP core 256
Update : 2025-02-17 Size : 130kb Publisher : weipingzhang
[VHDL-FPGA-Verilog] aes_core DL : 0: aes 加密模块，通过这个例子可以学习专业集成电路设计中数字电路设计的一些方法，带你入门设计-aes encryption module can learn through the example of professional digital circuit design integrated circuit design in some way, take you on design
Update : 2025-02-17 Size : 321kb Publisher : ssy
[Linux-Unix] aes_core DL : 0: Note: rewritten a little bit to provide error control and an OpenSSL- compatible API.
Update : 2025-02-17 Size : 12kb Publisher : waimamon
[Crack Hack] aes_core DL : 0: aes加密解密核,验证可用，可仿真，代码简洁，适合学习-aes core
Update : 2025-02-17 Size : 77kb Publisher : liujiwei
[VHDL-FPGA-Verilog] AES_core DL : 0: 蓝牙AES编码，希望对深入了解蓝牙开发的人有帮助-Bluetooth AES coding, and I hope people understand Bluetooth development help
Update : 2025-02-17 Size : 7kb Publisher : 李华