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[VHDL-FPGA-Verilog] arm9verilog

Description: AMBA AHB verilog Source code
Platform: | Size: 195584 | Author: Frank Chen | Hits:

[VHDL-FPGA-Verilog] AHB_to_Wishbone_Verilog

Description: 该源代码包是AHB总线到Wishbone总线的交接器，包括以下4个部分：RTL源代码，测试平台，软件测试程序，说明文档。-This source package is the AHB bus to Wishbone bus bridge(wrapper).It has the following 4 parts: RTL codes, testbench, software simulating files, help documents.
Platform: | Size: 2077696 | Author: jinjin | Hits:

[VHDL-FPGA-Verilog] wb_to_amba_latest[1].tar

Description: ahb总线到wishbone总线的桥接器，包括一个testbench,该版本暂不支持burst操作-A AHB master to WishBone slave bridge along with a basic testbench is included. Burst in not yet supported
Platform: | Size: 11264 | Author: hxr | Hits:

[Industry research] ahbTestbench_obf

Description: Verilog AHB Testbench
Platform: | Size: 145408 | Author: Liu, Cheng | Hits:

[Other] AHB RAM

Description: Verilog写的 AHB总线接口的SRAM代码，带Testbench。(Verilog wrote AHB bus interface SRAM code with Testbench.)
Platform: | Size: 21811200 | Author: 容止 | Hits:

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