Search - algorithm verilog

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[Crack Hack] MD5(verilog) DL : 0: MD5算法的verilog实现，同时包含有testbench。-Verilog of MD5 algorithm is realized, includes testbench at the same time .
Date : 2025-07-03 Size : 4kb User : 张雷
[VHDL-FPGA-Verilog] des-verilog DL : 1: des加密算法的verilog语言的实现-des encryption algorithm to achieve the Verilog language
Date : 2025-07-03 Size : 66kb User : 杨云丰
[Crack Hack] aes_core DL : 0: AES高级加密算法的verilog语言实现。同时附有AES协议的pdf文档，和此代码的测试程序，可作为一个IP核直接使用，可减少开发人员的设计时间。-AES Advanced Encryption Algorithm Verilog language. While the agreement with AES pdf documents, and that this code of the test procedure can be used as an IP core direct use, developers can reduce design time.
Date : 2025-07-03 Size : 78kb User :
[Books] 030413 DL : 0: 一篇基于小波变换的使用SPIHT算法进行图像压缩的文章-one based on wavelet transform SPIHT the use of image compression algorithm for the article
Date : 2025-07-03 Size : 197kb User : b
[VHDL-FPGA-Verilog] Viterbi_v DL : 0: Viterbi算法的Verilog源代码。-Viterbi Algorithm Verilog source code.
Date : 2025-07-03 Size : 11kb User : qjyong
[VHDL-FPGA-Verilog] verilog-som DL : 0: 拿verilog编写的som(自适应神经网络算法)，用于障碍物检测，基于FPGA可综合实验，已经在altera的cylcone上实现-Canal verilog prepared som (adaptive neural network algorithm) for obstacle detection. Based on FPGA synthesis experiments, in altera achieve the cylcone
Date : 2025-07-03 Size : 5kb User : 刘索山
[Crack Hack] mini_aes DL : 0: aes算法的verilog hdl实现，供给大家作为参考。-Orangk'aes algorithm verilog hdl realized, we supply as a reference.
Date : 2025-07-03 Size : 235kb User : 杨忠宇
[Compress-Decompress algrithms] 601792346200732319490634862 DL : 0: jpeg压缩中的DCT蝶型算法verilog代码-jpeg DCT compression algorithm verilog code BUTTERFLY
Date : 2025-07-03 Size : 5kb User : wuguanying
[VHDL-FPGA-Verilog] magnitude DL : 0: Verilog HDL: Magnitude For a vector (a,b), the magnitude representation is the following: A common approach to implementing these arithmetic functions is to use the Coordinate Rotation Digital Computer (CORDIC) algorithm. The CORDIC algorithm calculates the trigonometric functions of sine, cosine, magnitude, and phase using an iterative process. It is made up of a series of micro-rotations of the vector by a set of predetermined constants, which are powers of two. Using binary arithmetic, this algorithm essentially replaces multipliers with shift and add operations. In a Stratix™ device, it is possible to calculate some of these arithmetic functions directly, without having to implement the CORDIC algorithm. -Verilog HDL : For a vector magnitude (a, b), the magnitude representation is the following : A common approach to implementing thes e arithmetic functions is to use the Coordinate Rotation Digital Computer (CORDIC) algorithm. The CORDIC algorithm calculates the trigonome tric functions of sine, cosine, magn itude, and phase using an iterative process. It i 's made up of a series of micro-rotations of the v ector by a set of predetermined cons tants, which are powers of two. Using binary ar praxiology metic, this algorithm essentially replaces m ultipliers with shift and add operations. In a Stratix
Date : 2025-07-03 Size : 12kb User : 郝晋
[Special Effects] DCTofJPEG DL : 0: 用verilog代码写的JPEG压缩核心模块DCT变换之蝶形单元算法-verilog code written using JPEG compression core module DCT's butterfly modules algorithm
Date : 2025-07-03 Size : 1kb User : 叶人杰
[Other Embeded program] fpga-jpeg-verilog DL : 0: fpga-jpeg-verilog在fpga平台使用verilog语言进行jpeg算法实现-fpga-jpeg-verilog FPGA platform used in the Verilog language Algorithm jpeg
Date : 2025-07-03 Size : 102kb User : yang
[Crack Hack] verilog DL : 0: 用于aes128加密的扩展密钥算法，比较详细-For the expansion of key aes128 encryption algorithm, a more detailed
Date : 2025-07-03 Size : 11kb User : zsh
[VHDL-FPGA-Verilog] sinfunction DL : 0: 用cordic算法实现超越函数,sin,cos用此方法也可以实现其他的sinhx,coshx,ex.代码用verilog编写-CORDIC algorithm with transcendental function, sin, cos by this method can also realize other sinhx, coshx, ex. Verilog code used to prepare
Date : 2025-07-03 Size : 231kb User : yu_leo
[VHDL-FPGA-Verilog] cordic DL : 0: cordic verilog 程序及仿真结果 8级流水线-cordic verilog simulation results procedures and eight lines
Date : 2025-07-03 Size : 1kb User : elisen
[Compress-Decompress algrithms] dwt(SPIHT256) DL : 0: 可用的基于小波的spiht算法，可以自己设定小波分解基数，做成人机交互界面，直观-Available to the SPIHT algorithm based on wavelet, wavelet decomposition can be set for the base, resulting in human-computer interaction interface, intuitive
Date : 2025-07-03 Size : 3.87mb User : 李雨
[Crack Hack] DES DL : 0: DES算法的verilog实现，实现了硬件IC对DES的构架，可以直接应用在系统当中。-DES algorithm Verilog realized, the realization of the hardware IC framework of DES, can be directly used in the system.
Date : 2025-07-03 Size : 10kb User : 金鑫
[Special Effects] butterfly-verilog DL : 0: VHDL的DCT变换.蝶型算法,很好用的,希望能有帮助-The DCT transform VHDL. Butterfly algorithm, very good with the hope that it can be helpful
Date : 2025-07-03 Size : 1kb User : zhaoyizhi
[CA auth] md5_latest[1][1].tar DL : 0: MD5算法verilog代码，很不错的，可以互相交流学习-MD5 algorithm verilog code, and a very good
Date : 2025-07-03 Size : 15kb User : 朱坤旺
[VHDL-FPGA-Verilog] Verilog DL : 0: 用verilog实现七位最大公约数的算法，使用状态机，可仿真电路图-Seven with the greatest common divisor algorithm verilog implementation, the use of state machine circuit simulation
Date : 2025-07-03 Size : 317kb User : LEEY
[Other] SM3算法verilog实现 DL : 0: SM3算法verilog实现,利用alter芯片开发的sm3算法实现(Implementation of SM3 algorithm Verilog and implementation of Sm3 algorithm developed by alter chip)
Date : 2025-07-03 Size : 3kb User : rymm

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