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[VHDL-FPGA-Verilog] Altera_uart_VHDL

Description: FPGA/CPLD应用,uart通讯VHDL原码.-FPGA/CPLD applications, UART communications VHDL source.
Platform: | Size: 10240 | Author: cyberworm | Hits:

[Other] uart_IP

Description: altera 的uart ip核，可直接调用 在quartus中把库指向文件位置就可-altera the uart ip nuclear, can be directly called in the Quartus point in the database file location can be
Platform: | Size: 5120 | Author: 李涛 | Hits:

[VHDL-FPGA-Verilog] 16550

Description: UART16550兼容的串行通讯控制器，Verilog语言描述，采用Altera Cyclone系列芯片实现FPGA综合，因为FIFO部分利用到内部资源实现。已经在某项目中成功应用，特此推出。-UART16550 compatible serial communication controller, Verilog language description, the use of Altera Cyclone series FPGA chip integrated, as part of the use of FIFO to the internal resources to achieve. Projects have been in a successful application, is hereby introduced.
Platform: | Size: 10240 | Author: David.Mr.Liu | Hits:

[VHDL-FPGA-Verilog] miniUART

Description: 自适应波特率的通用异步串行接口电路（ＵＡＲＴ）的ＶＨＤＬ源码，在ＡＬＴＥＲＡ上运行成功-Adaptive baud rate of the universal asynchronous serial interface circuit (UART) the VHDL source code, to run successfully in ALTERA
Platform: | Size: 9216 | Author: 甘甜 | Hits:

[Software Engineering] 15Altera_IP

Description: 里面包含15个altera的IP核的源代码,包括I2C，UART，VGA_SYN-Which contains 15 nuclear altera the IP source code, including I2C, UART, VGA_SYN
Platform: | Size: 49152 | Author: hhl | Hits:

[VHDL-FPGA-Verilog] uart

Description: uart的vhdl实现，包含完整quartus工程文件，相信会有较大帮助-uart vhdl quartus
Platform: | Size: 212992 | Author: Carlin | Hits:

[VHDL-FPGA-Verilog] uart16450

Description: uart 16450合集,xilin altera lattice-collection of uart controller 16450
Platform: | Size: 822272 | Author: jhv | Hits:

[ARM-PowerPC-ColdFire-MIPS] uart

Description: 用ALTERA的芯片做的多串口代码，内部做了3个通用串口，适合51 ARM等CPU，有完整的ALTERA工程和仿真波形-uart FOR ALTERA
Platform: | Size: 1571840 | Author: 郭强 | Hits:

[VHDL-FPGA-Verilog] URAT_VHDL_CODE

Description: altera公司的fpga源代码，用VHDL编写的uart程序。-altera' s fpga source code, uart program written using VHDL.
Platform: | Size: 32768 | Author: 张东 | Hits:

[VHDL-FPGA-Verilog] SOPC_UART

Description: altera公司的ep1c240c8n，串口调试程序vhdl\nios ii8.0代码等-altera company ep1c240c8n, serial debugger vhdl \ nios ii8.0 code. .
Platform: | Size: 3193856 | Author: 张东 | Hits:

[VHDL-FPGA-Verilog] UART

Description: 异步串口收发程序，波特率4800。VHDL写成。在ALTERA开发板上测试成功。-This is a UART program, with a fixed 4800bps. Tested successfully on an Altera divice.
Platform: | Size: 1478656 | Author: 王羽 | Hits:

[VHDL-FPGA-Verilog] uart_lcd1602

Description: 点亮altera公司DE2代开发板的1602液晶，采用niosII方法。-Light the LCD1602 of the altera DE2 board with the niosII method
Platform: | Size: 9951232 | Author: 王郑帼 | Hits:

[VHDL-FPGA-Verilog] altera-uart

Description: ALTERA UART sopc 软核的VHDL描述-ALTERA UART VHDL DESCRIBE
Platform: | Size: 9216 | Author: pengli | Hits:

[Com Port] uart

Description: Code VHDL/Verilog for UART FPGA: Xilinx, Altera-Code VHDL/Verilog for UART FPGA: Xilinx, Altera...
Platform: | Size: 11264 | Author: NgocAnh | Hits:

[VHDL-FPGA-Verilog] UART-VHDL-QUARTUS

Description: uart vhdl quartus for altera
Platform: | Size: 212992 | Author: gilang | Hits:

[VHDL-FPGA-Verilog] uart_lcd

Description: 基于FPGA的UART通信，并用LCD(1602)显示通讯状态和通讯的数据。通过在ALTERA公司生产的DE2-115开发板上运行，证明此程序稳定可靠。时钟为50MHz，语言为VHDL,状态机。-FPGA-based UART communication, and LCD (1602) show the communication status and data communications. DE2-115 development board by ALTERA Company production run, prove that the program is stable and reliable. The clock is 50MHz, language VHDL, state machines.
Platform: | Size: 6435840 | Author: jiazhaorong | Hits:

[VHDL-FPGA-Verilog] IP

Description: USB+UART+I2C+VGA+ARM7+MC8051 altera IP核-USB+UART+I2C+VGA+ARM7+MC8051 Verrlog VHDL
Platform: | Size: 3806208 | Author: 刘春焱 | Hits:

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