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[VHDL-FPGA-Verilog] adma.tar

Description: 基于AMBA规范的总线VERILOG HDL 源代码-Based on the AMBA bus specification VERILOG HDL source code
Platform: | Size: 12288 | Author: maliang | Hits:

[Other] amba3core

Description: amba3 sva 完全验证的代码，有verilog的和systemverilog的-amba3 sva fully validate the code, and the Verilog and SystemVerilog
Platform: | Size: 280576 | Author: kevin | Hits:

[VHDL-FPGA-Verilog] CODE

Description: AHB总线下的slave ram的verilog代码-AHB bus slave ram verilog
Platform: | Size: 1024 | Author: 龙的传人 | Hits:

[VHDL-FPGA-Verilog] BP062-BU-01000-r0p0-00rel0[1][1].tar

Description: AXI协议检查器，由ARM公司开发对于想开发AXI master和slave模型的ASIC设计人员非常有用！-AXI protocol checker, developed by ARM to develop for the AXI master and slave model is very useful ASIC designers!
Platform: | Size: 313344 | Author: 李忠孝 | Hits:

[Windows Develop] System_Design_and_Implementation_of_AXI_Bus

Description: AMBA AXI资料，台湾硕士论文，网上收集-AMBA AXI, Taiwanese master' s thesis, on-line collection of
Platform: | Size: 1288192 | Author: kyle | Hits:

[VHDL-FPGA-Verilog] handshake

Description: AMBA 3 AXI handshake protocol. Verilog platform. master and slave.
Platform: | Size: 196608 | Author: nodeity | Hits:

[VHDL-FPGA-Verilog] Axi_mux

Description: The elements come from the necessity of creating generic modules, in the verification phase, for this widely used protocol. These primitives are presented as a not compiled library written in SystemC where interfaces are the core of the library. The definition of interfaces instead of generic modules let the user construct custom modules improving the resources spent during the verification phase as well as easily adapting his own modules to the AMBA 3 AXI protocol. As validation scenario, results obtained for an AXI bus connecting IDCT and other processing resources for MPEG4 video decoding are presented.
Platform: | Size: 41984 | Author: Paul Stephen | Hits:

[VHDL-FPGA-Verilog] ppt

Description: 介绍 AXI 协议的PPT, 和一个 slave（verilog实现） 接口的简单实现，需要的可以看看；-AXI protocol described PPT, and a slave interface is simple to achieve, need to look at
Platform: | Size: 637952 | Author: 周西东 | Hits:

[VHDL-FPGA-Verilog] AMBA_AHB.rar

Description: amba AHB coding in verilog HDL and integrating with AHB to AXI Brigde,amba AHB coding in verilog HDL and integrating with AHB to AXI Brigde
Platform: | Size: 5120 | Author: videv | Hits:

[source in ebook] AXI_MIG

Description: ISE生成的AXI接口的MIG，内存控制器，语言：verilog-ISE generated the AXI interface MIG, memory controller, language: verilog
Platform: | Size: 747520 | Author: 王小玲 | Hits:

[VHDL-FPGA-Verilog] verilog-master-files

Description: Verilog master files of AMBA axi interface
Platform: | Size: 26624 | Author: Sasanka | Hits:

[VHDL-FPGA-Verilog] AXI slave

Description: 使用verilog语言实现了AXI总线通信协议的从机部分(The slave part of AXI bus communication protocol is realized by using Verilog language)
Platform: | Size: 1024 | Author: 天地孤影i | Hits:

[VHDL-FPGA-Verilog] gpio_axi

Description: Zturn board - GPIO - AXI
Platform: | Size: 22609920 | Author: ratfink | Hits:

[VHDL-FPGA-Verilog] axi_ad9361

Description: AXI_AD9361 的 verilog 驱动工程，包含数据接收，数据发送 AXI总线 ，全部是verliog实现(AXI_AD9361's Verilog drive project, including data reception, data transmission AXI bus, all verliog implementation)
Platform: | Size: 40960 | Author: 大木瓜 | Hits:

[VHDL-FPGA-Verilog] AMBAaxi

Description: amba axi specification
Platform: | Size: 447488 | Author: kumaru | Hits:

[VHDL-FPGA-Verilog] axi_slave

Description: amba总线中axi的slave部分，用verilog实现的slave.(The slave part of Axi in the AMBA bus, slave. implemented with Verilog)
Platform: | Size: 1024 | Author: 过客3944 | Hits:

[VHDL-FPGA-Verilog] src

Description: 基于AXI 总线的可配置脉冲计数器，可以配置计算脉冲的个数。(The configurable pulse counter based on AXI bus can be configured to calculate the number of pulses)
Platform: | Size: 40960 | Author: ICwxforever | Hits:

[VHDL-FPGA-Verilog] my_led_ip

Description: 四通道axi LED灯控制器，用于嵌入式系统中的一些功能指示(The four channel Axi LED lamp controller is used for some function instructions in the embedded system)
Platform: | Size: 9216 | Author: ICwxforever | Hits:

[Other] new.v

Description: 状态机写的axi slave，模式较少，基本功能齐全，轻便,仿真综合通过(AXI4 slave programmed by state machine approach)
Platform: | Size: 1024 | Author: 风城复辟 | Hits:

[VHDL-FPGA-Verilog] verilog-axi-master

Description: Verilog AXI Components Readme GitHub repository: alexforencich verilog-axi
Platform: | Size: 313344 | Author: viyefo5674 | Hits:
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