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[SCM] c8051f-UART

Description: 软件UART示例 两个完整的例子,一个用PCA为波特率发生器的C语言程序和一个用定时器0为波特率发生器的汇编语言程序. 适用于下列器件 C8051F000C8051F001C8051F002C8051F005C8051F006C8051F010C8051F011C8051F012C8051F015C8051F016C8051F017C8051F220C8051F221C8051F226C051F230C8051F231C8051F236-Software UART Examples of two complete example, a baud rate generator with PCA for the C language program and a use timer 0 baud rate generator for the assembly language program. C8051F000C8051F001C8051F002C8051F005C8051F006C8051F010C8051F011C8051F012C8051F015C8051F016C8051F017C8051F220C8051F221C8051F226C051F230C8051F231C8051F236 applies to the following devices
Platform: | Size: 927744 | Author: fency | Hits:

[VHDL-FPGA-Verilog] VHDL_UART

Description: VHDL语言的UART串行接口芯片程序,包括数据接收器、数据发送器和波特率发生器等。-VHDL language UART serial interface chip procedure, including data receiver, data transmitter and baud rate generator and so on.
Platform: | Size: 3072 | Author: liukun | Hits:

[SCM] software-uart

Description: 软件UART程序，用PCA做波特率发生器，使用的是C8051F000单片机-Software UART procedure, PCA to do with the baud rate generator, using a single-chip C8051F000
Platform: | Size: 6144 | Author: 张雪梅 | Hits:

[Com Port] UART_51

Description: 串口设置：包括初始化及应用；串口调试方面直接能用上-// This sample uses the UART to communicate with a PC. Therefore it sets up the internal // Baud Rate Generator (BRG). The LPC900 receives a command ( S ), sent by the PC and // sends out a response, which can be displayed with the program Hyperterminal . // The parameter settings for // 9600 baud, 8 data bits, 1 stop bit and no flow control. // To begin the communication click on wait for call .
Platform: | Size: 1024 | Author: 罗岳 | Hits:

[Com Port] uart_zhiwen

Description: RS232的UART编程，包括波特率发生器模块，串口接受模块，串口发送模块-RS232 programming the UART, including the baud rate generator module, serial module to receive, send serial module
Platform: | Size: 109568 | Author: zhangyi | Hits:

[VHDL-FPGA-Verilog] uart

Description: 带自适应波特率发生器UART实现，经过FPGA验证的！-UART baud rate generator with adaptive realization, after FPGA validation!
Platform: | Size: 6144 | Author: guochao | Hits:

[SCM] c8051f-UART

Description: 本应用笔记讨论基于C8051Fxxx系列器件的软件UART实现方法本文给出两个完整的例子一个用PCA为波特率发生器的C语言程序和一个用定时器0为波特率发生器的汇编语言程序-Application Notes discuss the C8051Fxxx series of devices based on the software UART implementation integrity of this paper two examples of a baud rate generator with PCA for the C language program and a timer 0 with baud rate generator for the assembly language program
Platform: | Size: 927744 | Author: 赵箭 | Hits:

[VHDL-FPGA-Verilog] URAT_VHDL

Description: URAT VHDL程序与仿真，包括顶层程序与仿真，波特率发生器VHDL程序， UART发送器程序与仿真，UART接收器程序与仿真-URAT VHDL procedures and simulation, including the top-level procedures and simulation, VHDL program baud rate generator, UART transmitter and simulation program, UART receiver and simulation program
Platform: | Size: 32768 | Author: 葛棋棋 | Hits:

[VHDL-FPGA-Verilog] uart16550_latest[1].tar

Description: 开源UART IP核16550，该IP核兼容16550 UART，具有Modem功能，完全可编程的串行接口具有可设置的字符长度、奇偶校验、停止位以及波特率生成器。-Open-source UART IP core 16550, the IP core is compatible with 16550 UART, with Modem function, fully programmable serial interface can be set up with a character length, parity, stop bits and baud rate generator.
Platform: | Size: 1559552 | Author: lisa1027 | Hits:

[Embeded-SCM Develop] uart

Description: 一个串口程序，用定时器作为波特率发生器，只要知道波特率便可以直接初使化uart，具有很强的适应能力的程序-A serial program, with the timer as a baud rate generator, as long as they can directly know the baud rate initialization uart, has a strong ability to adapt procedures
Platform: | Size: 4096 | Author: gj | Hits:

[VHDL-FPGA-Verilog] URAT_transmitter_receiver_VHDL

Description: 基于UART的VHDL程序，包括顶层程序、波特率发生器程序、UART发送器程序、UART接收器程序4部分程序。有详细注释，并在每个程序后附上一张仿真波形图，便于理解和验证。-UART in VHDL-based procedures, including the top-level procedures, procedures for the baud rate generator, UART transmitter program, UART receiver program four part of the program. Detailed notes, and attached to each program a simulation waveform diagram, easy to understand and verify.
Platform: | Size: 36864 | Author: kuaile | Hits:

[Program doc] ADUC841--t3

Description: ADUC841串口通讯，c语言编写，用t3作为波特率发生器，电路外接晶振频率为11.0592MHZ.另外注意PLLCON寄存器可能需要在头文件中定义。-ADUC841 serial communication, c language, with t3 as the baud rate generator, an external crystal frequency Circuit 11.0592MHZ. Also note that PLLCON registers may need to define in the header file.
Platform: | Size: 1024 | Author: 黄超 | Hits:

[SCM] UART

Description: LYS-51开发板串口通信驱动，包括初始化，写字节，写字串函数。在12m晶振下，使用Timer2作为波特率发生器。-LYS-51 development board serial communication drivers, including the initialization, write byte, write string function. In the 12m crystal, the use Timer2 as a baud rate generator.
Platform: | Size: 1024 | Author: | Hits:

[VHDL-FPGA-Verilog] UART_verilog

Description: 带波特率发生器的FPGA_UART串口通信代码，使用ISE10.1综合应用过，通过计算调整两个参数baud_frequcy,baud_limit可适用于多种波特率下的UART传输-With a baud rate generator FPGA_UART serial communication code, use ISE10.1 integrated application before, by calculating the adjusted two parameters baud_frequcy, baud_limit applicable to a variety of baud rate, UART
Platform: | Size: 373760 | Author: rick lee | Hits:

[VHDL-FPGA-Verilog] uart

Description: 串口通信控制器的Verilog实现。包含4个模块：顶层模块、波特率发生器模块、发送模块和接收模块-The serial communication controller Verilog. Contains four modules: the top-level module, the baud rate generator module, transmitting module and receiver module
Platform: | Size: 3072 | Author: 王帆淼 | Hits:

[Other] UART-DISPLAY

Description: lcd 显示，Verilog语言，串口接收数据，并在LCD中显示，波特率9600，包括主文件，LCD控制文件，波特率发生文件-lcd display Verilog language, serial port to receive data, and the LCD display, baud rate of 9600, including the master file, the LCD control file, the baud rate generator file
Platform: | Size: 533504 | Author: jsquare | Hits:

[SCM] MSP430-uart

Description: 430 UART程序实例 包括初始化代码设置，中断方法实现-Description: This program demonstrates a half-duplex 2400-baud UART using Timer_A3 and a 32kHz crystal. The program will wait in LPM3, echoing back a received character using 8N1 protocal. The 32768 crystal is used directly as the Timer_A clock and baud rate generator.
Platform: | Size: 3072 | Author: fzgh | Hits:

[VHDL-FPGA-Verilog] UART

Description: URAT设计，系统包括五个模块，MCU模块，TX发送模块，RX接受模块，波特率产生模块，复位模块。-URAT design, the system consists of five modules, MCU module, TX transmit module, RX accept modules, baud rate generator module, reset module.
Platform: | Size: 56320 | Author: 李龙 | Hits:

[VHDL-FPGA-Verilog] uart

Description: 本例程是用verilog硬件描述语言在quaryusII环境下开发的串口通信模块，分为发送模块，接受模块和波特率产生模块。-This routine is verilog hardware description language development environment under quartus II serial communication module, divided into send module, receive module and baud rate generator module.
Platform: | Size: 276480 | Author: PrudentMe | Hits:

[VHDL-FPGA-Verilog] UART

Description: verilogHDL语言实现的uart模块，内部包含波特率生成、uart收、uart发三个子模块，支持配置常规波特率、数据位、结束位和校验位，输入工作时钟125M，时钟不一样时需要修改波特率生成的代码-verilogHDL language of uart module contains an internal baud rate generator, uart receive, uart made three sub-module, configured to support conventional baud rate, data bits, stop bits and parity bits, input operation clock 125M, the clock is not the same when needed change the baud rate generated code
Platform: | Size: 6144 | Author: 沈浩 | Hits:
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