Description: URAT VHDL procedures and simulation, including the top-level procedures and simulation, VHDL program baud rate generator, UART transmitter and simulation program, UART receiver and simulation program
- [UART] - Input clock 20M, the baud rate for 9600,
- [URAT] - URAT the VHDL design and timing simulati
- [uart_tran] - Verilog UART serial transmission of the
- [receive] - CC1100and STC89C54,using for the remote
- [uart_vhdl] - UART VHDL
- [cameralink] - As the CameraLink interface is currently
- [mem_ctrl_latest.tar] - FPGA memory control processes, including
- [rs232] - Realized in the FPGA serial data transmi
- [rs232] - Vhdl fpga serial communication with the
File list (Check if you may need any files):
URAT_VHDL .doc
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