Search - binary to BCD vhdl

[SCM] VHDL范例

Description: 最高优先级编码器 8位相等比较器三人表决器（三种不同的描述方式）加法器描述 8位总线收发器：74245 （注2）地址译码（for m68008）多路选择器（使用select语句） LED七段译码多路选择器（使用if－else语句）双2－4译码器：74139 多路选择器（使用when－else语句）二进制到BCD码转换多路选择器（使用case语句）二进制到格雷码转换双向总线（注2）汉明纠错吗译码器三态总线（注2）汉明纠错吗编码器解复用器 -highest priority encoder, compared to eight for phase three of the vote (the description of three different ways) Adder Description eight bus Transceivers : 74,245 (Note 2) address decoder (for m68008) Multiple choice (use select statement) LED paragraph 107 of decoding multiple choice ( use if-else statements) 2-4 dual decoder : over 74,139 road choice (use when-else statements) of the binary conversion BCD multiple choice (use case statement) binary Gray code conversion to a two-way bus (Note 2)? Hamming error correction decoder three-state Bus (Note 2)? Hamming error correction encoder demultiplexer
Platform: | Size: 43008 | Author: kerty | Hits:

[VHDL-FPGA-Verilog] Verilog_Development_Board_Sources

Description: 朋友，我是Jawen.看到先前上载的一套CPLD开发板的VHDL源码挺受欢迎的，现在就将她的Verilog源码也一并贡献给大家：8位优先编码器,乘法器,多路选择器,二进制转BCD码,加法器,减法器,简单状态机,四位比较器,7段数码管,i2c总线,lcd液晶显示,拨码开关,串口,蜂鸣器,矩阵键盘,跑马灯,交通灯,数字时钟-friends, I Jawen. previously seen on the set of CPLD Development Board VHDL source code quite welcome, Now she will also be Verilog source contribution to everyone : eight priority encoder, multipliers, Multi-channel selector, binary to BCD, adder, subtraction device, the simple state machine, four comparators, 7 of the digital control, i2c bus, lcd LCD allocated code switches, serial port, the buzzer sounded, matrix keyboards, Bomadeng. Traffic lights, digital clock
Platform: | Size: 3151872 | Author: Jawen | Hits:

[MPI] add_16_bcd

Description: 此程序采用VHDL语言，完成在16位十六进制加法器的基础上将输出进行BCD码转换，实现输出是BCD码的16位二进制加法器-This procedure using VHDL language, completed in 16-bit hexadecimal adder based on output BCD code conversion, the realization of output is BCD code of 16 binary adder
Platform: | Size: 1024 | Author: 韩善华 | Hits:

[VHDL-FPGA-Verilog] add_32_bcd

Description: 此程序采用VHDL语言，完成在32位十六进制加法器的基础上将输出进行BCD码转换，实现输出是BCD码的32位二进制加法器-This procedure using VHDL language, completed in 32-bit hexadecimal adder based on output BCD code conversion, the realization of output is BCD code of 32 binary adder
Platform: | Size: 1024 | Author: 韩善华 | Hits:

[Other] Trafficlight

Description: 系统设置一个两位BCD码倒计时计数器（计数脉冲1HZ），用于记录各状态持续时间；因为各状态持续时间不一致，所以上述计数器应置入不同的预置数；倒计时计数值输出至二个数码管显示；程序共设置4个进程： ① 进程P1、P2和P3构成两个带有预置数功能的十进制计数器，其中P1和P3分别为个位和十位计数器，P2产生个位向十位的进位信号； ② P4是状态寄存器，控制状态的转换，并输出6盏交通灯的控制信号。-System to set up a two BCD code countdown counter (count pulse 1HZ), used to record the duration of each state because the duration of each state are inconsistent, so these counters should be placed in several different presets countdown of numerical output to two digital display procedures were set up four processes: ① process P1, P2 and P3 form two functions with a preset number of decimal counters, of which P1 and P3, respectively, for months, and 10-bit counters, P2 to generate a 10-bit The binary signal ② P4 is the status register, control the state of the conversion, and six output control signals of traffic lights.
Platform: | Size: 1024 | Author: kid | Hits:

[Other] binarytobcd

Description: 实现二进制到BCD的转换,相关算法可参考相关文档资料-convert binary number to BCD
Platform: | Size: 3072 | Author: CoCo | Hits:

[SCM] binarytobcd_arithmetic

Description: Binary to BCD arithmetic. 这东西真不错-Binary to BCD arithmetic. This is something really good
Platform: | Size: 3072 | Author: Reguse | Hits:

[VHDL-FPGA-Verilog] bin2bcd

Description: Binary to BCD converter
Platform: | Size: 1024 | Author: Natacho | Hits:

[VHDL-FPGA-Verilog] BIN_BCD

Description: 用硬件描述语音实现二进制数据转换成BCD数据-Using hardware description voice to achieve the binary data into BCD data
Platform: | Size: 620544 | Author: sleeeeeeep | Hits:

[VHDL-FPGA-Verilog] HEX2BCD

Description: 基于fpga的二进制和BCD骂转换模块vhdl描述，只需修改相关参数即可使用-Fpga-based binary and BCD conversion module called vhdl description, simply modify the relevant parameters to use
Platform: | Size: 1024 | Author: 郭帅 | Hits:

[VHDL-FPGA-Verilog] Binary_to_BCD_Converter

Description: General Binary-to-BCD Converter The linked code is a general binary-to-BCD Verilog module, and I have personally tested the code.
Platform: | Size: 25600 | Author: volkan | Hits:

[VHDL-FPGA-Verilog] HEX2BCD16

Description: 基于vhdl的二进制转BCD码的设计，已经经过调试，可直接使用-Vhdl based on binary code to BCD design, has been testing can be used directly
Platform: | Size: 1024 | Author: 郭帅 | Hits:

[SCM] 4_in_1_converter

Description: this program can convert binary --> gray binary --> BCD BCD --> XS3 Gray --> binary... inputs will be of 4 bits for each converter.. If you have any doubt,then mail me at prem_bombay@yahoo.co.in -this program can convert binary--> gray binary--> BCD BCD--> XS3 Gray--> binary... inputs will be of 4 bits for each converter.. If you have any doubt,then mail me at prem_bombay@yahoo.co.in
Platform: | Size: 1024 | Author: Sumit | Hits:

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[SCM] VHDL范例

[VHDL-FPGA-Verilog] Verilog_Development_Board_Sources

[MPI] add_16_bcd

[VHDL-FPGA-Verilog] add_32_bcd

[Other] Trafficlight

[Other] binarytobcd

[SCM] binarytobcd_arithmetic

[VHDL-FPGA-Verilog] bin2bcd

[VHDL-FPGA-Verilog] BIN_BCD

[VHDL-FPGA-Verilog] HEX2BCD

[VHDL-FPGA-Verilog] Binary_to_BCD_Converter

[VHDL-FPGA-Verilog] HEX2BCD16

[SCM] 4_in_1_converter

[assembly language] binarytobcd

[VHDL-FPGA-Verilog] BCD

[VHDL-FPGA-Verilog] 2-Decimal-BCD-Decoder

[VHDL-FPGA-Verilog] bin2bcd

[VHDL-FPGA-Verilog] vhdl

[Software Engineering] 8421BCD

[Other] binary-to-bcd

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