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[VHDL-FPGA-Verilog] viterbi_for_bch

Description: Viterbi based trellis decoder for (7,4) - binary BCH code-Viterbi based trellis decoder for (7,4)- binary BCH code
Platform: | Size: 1024 | Author: shahifaqeer | Hits:

[VHDL-FPGA-Verilog] vhdlchufaqi

Description: 这是一个基于VHDL语言的bch除法器，其功能就是实现二进制除法，采用移位的方式进行-This is based on VHDL language bch divider, its function is to achieve binary division, the way by shift
Platform: | Size: 1024 | Author: 刘某 | Hits:

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