Search - bit sync

[Other] S3C44B0X中文技术文档

Description:

介绍

三星的S3C44B0X 16/32位RISC处理器被设计来为手持设备等提供一个低成本高性能的方案。

S3C44B0X提供以下配置：2.5V ARM7TDMI 内核带有8Kcache ;可选的internal SRAM;LCD Controller(最大支持256色STN，使用LCD专用DMA)；2-ch UART with handshake(IrDA1.0, 16-byte FIFO) / 1-ch SIO； 2-ch general DMAs / 2-ch peripheral DMAs with external request pins； External memory controller (chip select logic, FP/ EDO/SDRAM controller)； 5-ch PWM timers & 1-ch internal timer；Watch Dog Timer；71 general purpose I/O ports / 8-ch external interrupt source； RTC with calendar function； 8-ch 10-bit ADC； 1-ch multi-master IIC-BUS controller； 1-ch IIS-BUS controller； Sync. SIO interface and On-chip clock generator with PLL.。

S3C44B0X采用一种新的三星ARM CPU嵌入总线结构-SAMBA2，最大达66MHZ。

Platform: | Size: 78690 | Author: ssunshine | Hits:

[VHDL-FPGA-Verilog] FPGA_bit_clock_data_recovery

Description: 基于FPGA的新型数据位同步时钟提取(CDR)实现方法-New FPGA-based data bit sync clock extraction (CDR) method
Platform: | Size: 93184 | Author: sam zeng | Hits:

[Compress-Decompress algrithms] Signal

Description: 接收器必须具有某种方法能够知道数据流中字节的起始和结束。在异步通信中，字节边界由起始和停止位指示。在同步通信中，定时机制帮助发送器和接收器处于同步状态。-The receiver must have some way to know the data stream in bytes of the start and end. In asynchronous communication, the byte boundary from the start and stop bit instructions. In synchronous communication, the timing mechanism to help the transmitter and receiver are in sync.
Platform: | Size: 104448 | Author: 小柳 | Hits:

[Streaming Mpeg4] tsAdvance

Description: tsAdvance TS流操作软件，根据指定的音频PID统计码率，根据指定的PCR的PID统计码率，根据指定的视频PID统计码率，检查指定PID的连续计数，列出不连续的包位置，显示指定PID的各个DTS值，显示指定PID的各个PCR值，统计同步字节错误，统计同步丢失错误，统计PSISI表格的Table id错误，保存指定音视频PID的ES到outfile文件中，统计指定音视频PID时间长度，进行文件分隔，删除文件中指定PID的数据，并另存等功能-tsAdvance TS stream operating software, according to the specified bit-rate audio PID statistics, according to the specified PCR-PID statistical rate, according to the specified bit rate video PID statistics, check the continuous count of the specified PID, list location of discrete packets, showing the specified PID value of each DTS, showing the specified PID value of each PCR, statistical sync byte errors, statistical sync loss errors, statistical PSISI table Table id error, save the specified audio and video PID of the ES to the outfile file, specify the audio and video statistics PID length of time to file separate, delete the file specified in the PID of the data, and save functions
Platform: | Size: 273408 | Author: wutong | Hits:

[matlab] frame_syn

Description: 这是一个帧同步数据搜索模块，用于检测输入的数据流中的帧头，当检测到帧头后输出一个同步信号。输入数据为 8bit的并行数据流，数据流中的每帧由 10 个字节组成，为 1个字节的帧头（47H）加上 9 个字节的数据。各个字节的中间部分与时钟上升沿对齐。每帧数据中，除帧头外的其他数据也可能为 47H。在数据传输过程中，帧头数据有可能受到干扰而变为其他数值，因此要求输出同步信号时具有一定的容错功能。-This is a frame synchronization data search module, for detecting the input data stream in the frame header, when the detected frame header and a synchronization signal after the output. 8bit parallel input data for the data flow, data flow in each frame consists of 10 bytes for a byte frame header (47H) plus 9 bytes of data. The middle part of each byte alignment with the clock rising edge. Each frame of data, in addition to other data outside the frame header may 47H. In the data transmission process, the frame header data may be subject to interference into other values, thus requiring the output sync signal has certain fault tolerance.
Platform: | Size: 409600 | Author: 追月 | Hits:

[Graph program] 1

Description: 图像处理，RS编码，纠错码这个单元对每个扰码后的传输数据帧,包括同步字节进行截短的RS(204,188)编码.RS编码时, 在信息位前添加51字节的“0”再进入RS(255,239) 编码器,编码后再截去这些字节.RS(255,239)编码 -Image processing, RS coding, error correction code for each scrambling code of this unit after the transmission of data frames, including the sync byte truncated RS (204,188) code. RS encoding, the information bit before adding 51 bytes " 0 " and then enter the RS (255,239) encoder, encoding the bytes and then amputated. RS (255,239) coding
Platform: | Size: 1024 | Author: zrq | Hits:

[VHDL-FPGA-Verilog] 8bit_up_ise9migration

Description: sync ram of 258*8 bit you know
Platform: | Size: 997376 | Author: vishwas | Hits:

[matlab] b911a3340926

Description: Matlab video anlaysis A packet is the basic unit of data in a transport stream. It consists of a sync byte, whose value is 0x47, followed by three one-bit flags and a 13-bit Packet Identifier (PID). This is followed by a 4-bit continuity counter. -Matlab video anlaysis A packet is the basic unit of data in a transport stream. It consists of a sync byte, whose value is 0x47, followed by three one-bit flags and a 13-bit Packet Identifier (PID). This is followed by a 4-bit continuity counter.
Platform: | Size: 27648 | Author: sakthivel | Hits:

[SCM] manchester-coding

Description: 使用51单片机进行曼彻斯特编解码，编码程序中有同步头，结束位设置，解码有查找同步头，有效跳变检测等程序，内有proteus仿真原理图-With 51 single-chip codec to Manchester, there are sync, the end bit is set, decode sync with search, detection procedures are not effective, there proteus simulation schematic
Platform: | Size: 12288 | Author: 管俊波 | Hits:

[VHDL-FPGA-Verilog] frame-synchronous-search-circuit

Description: 用verilog语言编写的帧同步搜索电路，输入数据data为8 bit并行数据流，基本结构为数据帧，帧长为10字节，帧同步字为H“FF”。clk为输入同步时钟。-Verilog language for frame synchronous search circuit, the input data is data for the 8-bit parallel data stream, the basic structure of the data frame, the frame length of 10 bytes, the frame synchronization word H "FF". clk to input sync clock.
Platform: | Size: 420864 | Author: 眭明 | Hits:

[VHDL-FPGA-Verilog] serial

Description: 本模块的功能是验证实现和PC机进行基本的串口通信的功能。需要在PC机上安装一个串口调试工具来验证程序的功能。程序实现了一个收发一帧10个bit（即无奇偶校验位）的串口控制器，10个bit是1位起始位，8个数据位，1个结束位。串口的波特律由程序中定义的div_par参数决定，更改该参数可以实现相应的波特率。程序当前设定的div_par 的值是0x104，对应的波特率是9600。用一个8倍波特率的时钟将发送或接受每一位bit的周期时间划分为8个时隙以使通信同步-The module' s function is to verify the basic realization and PC serial communication functions. Required on the PC to install a serial debugging tools to verify functionality of the program. Program implements a transceiver a 10 bit (ie, no parity bit) serial controller, 10 bit is a start bit, 8 data bits, 1 stop bit. Baud-law by the parameters defined in the program div_par decision to change the parameters of the corresponding baud rate can be achieved. Program is currently set div_par value is 0x104, corresponding to the baud rate is 9600. 8 times the baud rate with a transmit or receive clock cycle time of each bit is divided into eight time slots to the communication sync
Platform: | Size: 354304 | Author: | Hits:

[VHDL-FPGA-Verilog] uart-to-GPIO.vhd

Description: -- Filename ﹕ uart.vhd -- Author ﹕ZRtech -- Description ﹕串口接收与发送程序 -- 本模块的功能是验证实现和PC机进行基本的串口通信的功能。需要在PC机上安装一个串口调试工具来验证-- 程序的功能。程序实现了一个收发一帧10个bit（即无奇偶校验位）的串口控制器，10个bit是1位起始位-- 8个数据位，1个结束位。串口的波特律由程序中定义的div_par参数决定，更改该参数可以实现相应的波-- 特率。程序当前设定的div_par 的值是0x145，对应的波特率是9600。用一个8倍波特率的时钟将发送或接-- 受每一位bit的周期时间划分为8个时隙以使通信同步. -- Called by ﹕Top module -- Revision History ﹕10-5-20 -- Revision 1.0 -- Company ﹕ ZRtech Technology .Inc -- Copyright(c) 2010, ZRtech Technology Inc, All right reserved-- Filename: uart.vhd- Author: ZRtech- Description: serial port receive and transmit programs- the function of this module is to verify the basic realization and PC serial communication functions. Need to install one on the PC serial port debugging tool to verify- program function. Program implements a transceiver a 10 bit (ie, no parity bit) serial controller, 10 bit is a start bit- 8 data bits, 1 stop bit. Baud-law by the parameters defined in the program div_par decision to change the parameter can achieve the corresponding wave- special rates. Program is currently set div_par value is 0x145, corresponding to the baud rate is 9600. 8 times the baud rate by a clock to transmit or- by the cycle time of each bit is divided into eight time slots to the communication sync.- Called by: Top module- Revision History :10-5- 20- Revision 1.0- Company: ZRtech Technology. Inc- Copyright (c) 2010, ZRtech Technology Inc, All right reserved
Platform: | Size: 3072 | Author: hj | Hits:

[VHDL-FPGA-Verilog] verilog-up-counter

Description: Verilog code for 4 bit Sync Up Counter
Platform: | Size: 11264 | Author: cmags | Hits:

[Linux-Unix] arm-ccn

Description: Bit shifts and masks in these defines must be kept in sync with arm_ccn_pmu_config_set() and CCN_FORMAT_ATTRs below.
Platform: | Size: 9216 | Author: ksfierie | Hits:

[Linux-Unix] vpfe_types

Description: YCbCr - 16 bit with external sync.Logical object volume layer. This layer implements data striping (raid0).
Platform: | Size: 8192 | Author: duemqcue | Hits:

[source in ebook] lut3sym_1bitDiff_AccuSync_new0312

Description: 这个函数用于通信信号的一比特查分解调，并实现信号的同步-This function is used to check one bit of the communication signal decomposition tune and sync signals
Platform: | Size: 5120 | Author: kei | Hits:

[SCM] c8051f020-ADS1248

Description: C8051F020驱动ads1248的源码；主要特性 ·具有 24 位分辨率、2 kSPS 数据速率以及 2.56 mW 功耗； ·4 组差动/7组单端输入 (ADS1248)；2 组差动/3组单端输入 (ADS1247) ·50/60 Hz同步抑制模式； ·低噪声可编程增益放大器(G=128 时为 40 nV)。-C8051F020 driver ads1248 program source code, ads1248 Main features with 24-bit resolution, 2 kSPS data rate and power consumption of 2.56 mW - Group 4 differential/7 group of single-ended input (ADS1248) 2 Unit Differential/Single 3 groups ended input (ADS1247) · 50/60 Hz sync suppression mode low noise programmable gain amplifier (G = 128 when the 40 nV).
Platform: | Size: 5120 | Author: 王铁臣 | Hits:

[Embeded Linux] DS90UR910

Description: TI公司的DS90UR910Q芯片数据手册，非常强大的视频数据串并转换芯片。-The DS90UR910Q is an interface bridge chip that recovers data the FPD-Link II serial bit stream and converts into a Camera Serial Interface (CSI-2) format compatible with Mobile Industry Processor Interface (MIPI) specifications. It recovers the 24- or 18-bit RGB data and 3 video sync-signals the serial bit stream compatible to FPD-Link II serializers.
Platform: | Size: 212992 | Author: eezoo | Hits:

[Embeded-SCM Develop] STM32_NES_ppugba

Description: stm32f103 nes模拟器60帧有声音，声音播放可以是Timer+pwm+低通滤波器或者Timer+dac，没做同步，声音有点怪怪的，望同好改进后上传。现在这个做了同步的，声音好了很多(The STM32F103 NES emulator has 60 frames, and the sound playback can be Timer+pwm+, low pass filter, or Timer+dac, Do not sync, sounds a bit strange, with improved upload hope. Now this is synchronized, the sound is much better)
Platform: | Size: 382976 | Author: kkk123 | Hits:

[Other] Virual device drivers (Audio/RS232/HDD)

Description: Content: - SerialNull v1.7 - Serial Ports Emulator - Virtual Serial Ports Emulator (VSPE)- creating multiple virtual COM ports to send and receive data. Allows you to share physical data for several applications, display the port in a local network and create virtual parallel ports. Free version is only available for 32-bit OS. - HUBI'S MIDI LOOPBACK DEVICE V2.5 - Connect/Sync multiple MIDI programs + add MultiClient I/O for all MIDI drivers + MidiCable: simple MIDI application with Transformations and filter, SysEx thru. +Up to 4 ports with multi client IN/OUT, full SysEx support. Freeware. Virtual Audio Cable v4.6 - implements an idea of a physical interconnection cable applied to Windows audio applications. Each cable has a pair of audio ports, input and output. - WinVblock v0.0.1.8-DEV - driver, that emulate physical HDD using Hdd image file. (can be used for bootting Windows 2k/XP).
Platform: | Size: 3291134 | Author: SergeX31 | Hits:

Category

Source Code

Web/Internet

Develop Tools

Document

Other

Search in results

OS

Platform

Language

File Type

Search list