Description: 这个例子是讲述用VHDL实现布斯算法，应该有点用，是我的研究生师哥给我的。-this case is about the use of VHDL Booth algorithm, should use a bit of my graduate students Shige to me. Platform: |
Size: 1897 |
Author:刘于 |
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Description: 一种可以完成16位有符号／无符号二进制数乘法的乘法器。该乘法器采用了改进的Booth算法，简化了部分积的符号扩展，采用Wallace树和超前进位加法器来进一步提高电路的运算速度。本乘法器可以作为嵌入式CPU内核的乘法单元，整个设计用VHDL语言实现。-a 16 to be completed with symbols / unsigned multiplication of the number of binary multipliers. The multiplier used to improve the Booth algorithm, simplified some of the plot symbols expansion Wallace tree and used-ahead adder circuit to further enhance the computing speed. The multiplier can be used as embedded CPU cores multiplication modules, the entire design with VHDL. Platform: |
Size: 19758 |
Author:李鹏 |
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Description: 这个例子是讲述用VHDL实现布斯算法，应该有点用，是我的研究生师哥给我的。-this case is about the use of VHDL Booth algorithm, should use a bit of my graduate students Shige to me. Platform: |
Size: 2048 |
Author:刘于 |
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Description: 一种可以完成16位有符号／无符号二进制数乘法的乘法器。该乘法器采用了改进的Booth算法，简化了部分积的符号扩展，采用Wallace树和超前进位加法器来进一步提高电路的运算速度。本乘法器可以作为嵌入式CPU内核的乘法单元，整个设计用VHDL语言实现。-a 16 to be completed with symbols/unsigned multiplication of the number of binary multipliers. The multiplier used to improve the Booth algorithm, simplified some of the plot symbols expansion Wallace tree and used-ahead adder circuit to further enhance the computing speed. The multiplier can be used as embedded CPU cores multiplication modules, the entire design with VHDL. Platform: |
Size: 19456 |
Author:李鹏 |
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Description: -- Booth Multiplier
-- This file contains all the entity-architectures for a complete
-- k-bit x k-bit Booth multiplier.
-- the design makes use of the new shift operators available in the VHDL-93 std
-- this design passes the Synplify synthesis check
-- download from: www.fpga.com.cn & www.pld.com.cn--- Booth Multiplier-- This file contains a ll the entity-architectures for a complete-- k- bit x k-bit Booth multiplier.-- the design mak es use of the new shift operators available in th e VHDL-93 std-- this design passes the Synplify synthesis check-- download from : www.fpga.com.cn Platform: |
Size: 2048 |
Author:罗兰 |
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Description: verilog程序，实现两个16bit数乘法，采用booth算法，基于状态机实现，分层次为datapath和controller两个子模块，testBench测试通过-verilog procedures, two 16bit multiplication, the algorithm used booth. Based on the state machine achieved at different levels for datapath controller and two sub-modules, testBench the test Platform: |
Size: 2048 |
Author: |
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Description: -- Booth Multiplier
-- This file contains all the entity-architectures for a complete
-- k-bit x k-bit Booth multiplier.
-- the design makes use of the new shift operators available in the VHDL-93 std
-- this design passes the Synplify synthesis check --- Booth Multiplier-- This file contains a ll the entity-architectures for a complete-- k- bit x k-bit Booth multiplier.-- the design mak es use of the new shift operators available in th e VHDL-93 std-- this design passes the Synplify synthesis check Platform: |
Size: 1024 |
Author:leanne |
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Description: 用VHDL语言编写的一个乘法器校程序
是基于BOOTH算法的 -VHDL language using a multiplier BOOTH school program is based on the algorithm Platform: |
Size: 1024 |
Author:杨天 |
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Description: 这是我用verilog hdl语言写的浮点乘法器,用的是基4的booth算法,对于部分积使用了5-2压缩和3-2压缩,欢迎大家指点,也欢迎大家把它改成流水线以提高速度.-This is my verilog hdl language used to write floating-point multiplier, using a Radix-4 algorithm for the booth for part of the plot using the 5-2 and 3-2 compression compression, welcomed everyone pointing, also welcomed the U.S. put it into a pipeline to improve speed. Platform: |
Size: 4096 |
Author:lanty |
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Description: 一个基于VerilogHDL语言的16位的booth算法的乘法器及其测试代码-VerilogHDL language based on the 16-bit multiplier of the booth algorithm and test code Platform: |
Size: 1024 |
Author:lixiang |
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Description: 潘明海 刘英哲 于维双 (论文)
中文摘要：
本文讨论了一种可在FPGA上实现的FFT结构。该结构采用基于流水线结构和快速并行乘法器的蝶形处理器。乘法器采用改进的Booth算法，简化了部分积符号扩展，使用Wallace树结构和4-2压缩器对部分积归约。以8点复点FFT为实例设计相应的控制电路。使用VHDL语言完成设计，并综合到FPGA中。从综合的结果看该结构可在XC4025E-2上以52MHz的时钟高速运行。在此基础上易于扩展为大点数FFT运算结构。
-Pan Minghai Liuying Zhe Yu-dimensional pairs (thesis) Chinese Abstract: This paper discusses an FPGA can be implemented on the structure of the FFT. The architecture based on pipeline architecture and fast parallel multiplier butterfly processor. Multiplier using modified Booth algorithm simplifying the partial product sign extension, use the Wallace tree and 4-2 compressor for partial product reduction. 8-point complex-point FFT as an example design of the corresponding control circuit. To complete the design using the VHDL language, and integrated into the FPGA. From the results of a comprehensive look at the structure can be XC4025E-2 with 52MHz clock on the high-speed operation. On this basis, easy to expand the structure for large point FFT operations. Platform: |
Size: 128000 |
Author:culun |
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Description: 利用BOOTH算法实现4位乘法运算，使乘法由简单的移位和加法完成。其中包含了MUL4源代码和Test代码，已通过仿真验证-BOOTH Algorithm 4 using multiplication, so that the shift from simple multiplication and addition completed. MUL4 which contains the source code and Test code has been verified by simulation Platform: |
Size: 6144 |
Author:邓军 |
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Description: 用vhdl实现的booth算法乘法器，包含了multiplexer和rca adder，同时提供了一个测试文件，modelsim测试通过-Algorithm with a booth multiplier vhdl implementation, including a multiplexer and rca adder, while providing a test file, modelsim test pass Platform: |
Size: 2048 |
Author:胡恩 |
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Description: this document describe a 8 * 8 bits mutiplier with vhdl using booth algorithm
and shown all parts of implementing this ip by ise software Platform: |
Size: 2065408 |
Author:seif |
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Search - booth algorithm vhdl