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[VHDL-FPGA-Verilog] FPGA_bit_clock_data_recovery

Description: 基于FPGA的新型数据位同步时钟提取(CDR)实现方法-New FPGA-based data bit sync clock extraction (CDR) method
Platform: | Size: 93184 | Author: sam zeng | Hits:

[Other] ATA_source_code

Description: ata控制器verilog源代码，入门的不错参考-ata controller Verilog source code, entry of a good reference
Platform: | Size: 789504 | Author: 范俊 | Hits:

[VHDL-FPGA-Verilog] auk_sdsdi

Description: 用于FPGA设计的代码（Verilog代码），在FPGA设计中的高速串并转换，时钟提取，对齐处理等功能-for FPGA design ,written by Verilog HDL the functions include SERDES , CDR and so on
Platform: | Size: 229376 | Author: 龙珠 | Hits:

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