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[VHDL-FPGA-Verilogcfft

Description: CFFT是一个数据宽度和点数都可配置的基4 FFT core,用VHDL实现-CFFT is a data width and the base points can be configured 4 FFT core, using VHDL realize
Platform: | Size: 168960 | Author: | Hits:

[VHDL-FPGA-Verilogcfft

Description: 用verilog语言编写的基4FFT,采用CORDIC算法实现的,仿真过,结果很好!-I use verilog language to design a FFT base 4,and use CORDIC arithmetic to achieve this. last , I test it, it looks very good
Platform: | Size: 13312 | Author: samu1 | Hits:

[VHDL-FPGA-VerilogcFFT

Description: CFFT is a radix-4 fast Fourier transform (FFT) core with configurable data width and a configurable number of sample points in the FFT. Twiddle factors are implemented using the CORDIC algorithm, causing the gain of the CFFT core to be different from the standard FFT algorithm. This variation in gain is not important for orthogonal frequency division modulation (OFDM) and demodulation. The gain can be corrected, to that of a conventional FFT, by applying a constant multiplying factor.
Platform: | Size: 183296 | Author: Nagendran | Hits:

[source in ebookpipelined_fft_128_latest.tar

Description: CFFT是一个数据宽度和点数都可配置的基4 FFT core,由于旋转因子是用CORDIC算法实现的,因此经过FFT后信号的增益和标准的FFT算法不同。但对于OFDM调制、解调等应用并不重要。由于增益是确定的,因此在输出时乘以确定常数即可等价标准的FFT。该FFT core的输入是正序的,输出是按照基4反序的-CFFT is a data width and number can be configured based 4 FFT core, due to the rotation factor is realized with CORDIC algorithm, so after FFT algorithm gain and standard signal after the FFT different. But is not essential for OFDM modulation, demodulation and other applications. The gain is determined, constant can be determined by multiplying the equivalent standard FFT so on output. The FFT core input is positive, the output is in accordance with the base 4 in reverse order
Platform: | Size: 218112 | Author: 阳辉 | Hits:

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